| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 01/14/2004 | CN1134790C Method for testing memory updating rate |
| 01/13/2004 | US6678860 Integrated circuit memory devices having error checking and correction circuits therein and methods of operating same |
| 01/13/2004 | US6678859 Optical disk apparatus and data reading method |
| 01/13/2004 | US6678852 Semiconductor device testing apparatus |
| 01/13/2004 | US6678850 Distributed interface for parallel testing of multiple devices using a single tester channel |
| 01/13/2004 | US6678845 Arrangement for testing programmed port registers of integrated network device by reading-back values from the port registers |
| 01/13/2004 | US6678836 Simple fault tolerance for memory |
| 01/13/2004 | US6678205 Multi-mode synchronous memory device and method of operating and testing same |
| 01/13/2004 | US6678195 Semiconductor memory device with improved flexible redundancy scheme |
| 01/08/2004 | WO2004003764A1 Method and apparatus for optimizing timing for a multi-drop bus |
| 01/08/2004 | WO2004003750A2 Error detection/correction code which detects component failure and which provides single bit error correction upon such detection |
| 01/08/2004 | WO2002086720A3 Method and apparatus for updating an error-correcting code during a partial line store |
| 01/08/2004 | US20040006730 Apparatus and method for testing on-chip ROM |
| 01/08/2004 | US20040006729 Hierarchical test methodology for multi-core chips |
| 01/08/2004 | US20040006727 Method and apparatus for testing multi-port memories |
| 01/08/2004 | US20040006680 Method and apparatus for generating deterministic, non-repeating, pseudo-random addresses |
| 01/08/2004 | US20040006441 Accuracy determination in bit line voltage measurements |
| 01/08/2004 | US20040006404 Permanent chip ID using FeRAM |
| 01/08/2004 | US20040004888 Scan path circuit and semiconductor integrated circuit comprising the scan path circuit |
| 01/08/2004 | US20040004879 Semiconductor integrated circuit device |
| 01/08/2004 | US20040004874 Circuit for generating trim bit signal in a flash memory device |
| 01/08/2004 | US20040004873 On-chip compression of charge distribution data |
| 01/08/2004 | US20040004872 System and method for identification of faulty or weak memory cells under simulated extreme operating conditions |
| 01/08/2004 | US20040004866 Semiconductor memory device with improved saving rate for defective chips |
| 01/08/2004 | US20040004864 On-die switchable test circuit |
| 01/08/2004 | US20040004854 Accelerated fatigue testing |
| 01/08/2004 | DE10305826A1 Magnetische Dünnfilmspeichervorrichtung mit Redundanzaufbau Thin film magnetic memory device having redundancy structure |
| 01/08/2004 | DE10229802B3 Testschaltung und Verfahren zum Testen einer integrierten Speicherschaltung Test circuit and method for testing an integrated circuit memory |
| 01/07/2004 | EP1377981A1 Method and system to optimize test cost and disable defects for scan and bist memories |
| 01/07/2004 | EP1377841A2 Low-jitter clock for test system |
| 01/07/2004 | EP1377840A2 Test system algorithmic program generators |
| 01/07/2004 | CN1466765A Writable tracking cells |
| 01/07/2004 | CN1466183A Method and device for burn-in testing SRAM |
| 01/07/2004 | CN1134017C Semiconductor device having semiconductor memory circuit to be tested |
| 01/07/2004 | CN1134015C Integrated storage unit having at least two slice frayments |
| 01/06/2004 | US6675336 Distributed test architecture for multiport RAMs or other circuitry |
| 01/06/2004 | US6675335 Method and apparatus for exercising external memory with a memory built-in self-test |
| 01/06/2004 | US6675334 Apparatus and method for multi-cycle memory access mapped to JTAG finite state machine with external flag for hardware emulation |
| 01/06/2004 | US6675329 Internal memory in application specific integrated circuit device and method for testing internal memory |
| 01/06/2004 | US6675319 Memory access and data control |
| 01/06/2004 | US6675272 Method and apparatus for coordinating memory operations among diversely-located memory components |
| 01/06/2004 | US6674682 Architecture, method(s) and circuitry for low power memories |
| 01/06/2004 | US6674677 Memory device tester and method for testing reduced power states |
| 01/06/2004 | US6674676 Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture |
| 01/06/2004 | US6674675 Semiconductor device with flexible redundancy system |
| 01/06/2004 | US6674674 Method for recognizing and replacing defective memory cells in a memory |
| 01/06/2004 | US6674673 Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture |
| 01/06/2004 | US6674667 Programmable fuse and antifuse and method therefor |
| 01/06/2004 | US6674377 Circuit, apparatus and method for improved current distribution of output drivers enabling improved calibration efficiency and accuracy |
| 01/06/2004 | US6674318 Semiconductor integrated circuit |
| 01/02/2004 | EP1376610A2 Block redundancy implementation in hierarchical RAMs |
| 01/02/2004 | EP1376609A2 Efficient column redundancy techniques |
| 01/02/2004 | EP1376597A2 Distributed, highly configurable modular address predecoder |
| 01/02/2004 | EP1376596A2 Synchronous global controller for enhanced pipeline |
| 01/02/2004 | EP1376329A2 Method of utilizing storage disks of differing capacity in a single storage volume in a hierarchic disk array |
| 01/02/2004 | EP1374250A2 Memory cell structural test |
| 01/02/2004 | EP1373913A1 Apparatus and method for testing circuit modules |
| 01/01/2004 | US20040003337 Error detection/correction code which detects and corrects component failure and which provides single bit error correction subsequent to component failure |
| 01/01/2004 | US20040003336 Error detection/correction code which detects and corrects memory module/transmitter circuit failure |
| 01/01/2004 | US20040003331 Method and apparatus for optimizing timing for a multi-drop bus |
| 01/01/2004 | US20040003315 Repairable block redundancy scheme |
| 01/01/2004 | US20040003170 Variable width content addressable memory device for searching variable width data |
| 01/01/2004 | US20040001432 Embedding a JTAG host controller into an FPGA design |
| 01/01/2004 | US20040001384 Semiconductor device |
| 01/01/2004 | US20040001377 Semiconductor memory device |
| 01/01/2004 | US20040001376 Method and design for measuring SRAM array leakage macro (ALM) |
| 01/01/2004 | US20040001375 Memory chip with test logic taking into consideration the address of a redundant word line and method for testing a memory chip |
| 01/01/2004 | US20040001369 Method for repairing memory cell |
| 01/01/2004 | US20040001366 Device and method for reading non-volatile memories having at least one pseudo-parallel communication interface |
| 01/01/2004 | US20040000932 Decoding circuit for wafer burn-in test |
| 12/31/2003 | WO2004001568A2 Single pin multilevel integrated circuit test interface |
| 12/31/2003 | WO2004001428A1 Test method for yielding a known good die |
| 12/31/2003 | CN2595198Y Detachable belt for swordsmanship garment |
| 12/31/2003 | CN1133174C Semiconductor memory device and method of burn-in testing |
| 12/31/2003 | CN1133173C 用于检测数字半导体电路装置的测试电路和方法 Test circuit and method for detecting digital semiconductor circuit device for |
| 12/31/2003 | CN1133172C 测试可读写的集成电子电路的总线接线的方法 Can read and write test integrated electronic circuits bus wiring method |
| 12/31/2003 | CN1133171C Test method for high speed memory devices by using clock modulation technique |
| 12/30/2003 | US6671845 Packet-based device test system |
| 12/30/2003 | US6671844 Memory tester tests multiple DUT's per test site |
| 12/30/2003 | US6671843 Method for providing user definable algorithms in memory BIST |
| 12/30/2003 | US6671842 Asynchronous bist for embedded multiport memories |
| 12/30/2003 | US6671837 Device and method to test on-chip memory in a production environment |
| 12/30/2003 | US6671836 Method and apparatus for testing memory |
| 12/30/2003 | US6671834 Memory redundancy with programmable non-volatile control |
| 12/30/2003 | US6671822 Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache |
| 12/30/2003 | US6671787 Semiconductor memory device and method of controlling the same |
| 12/30/2003 | US6671782 Method and apparatus for processing read requests in a shared disk system |
| 12/30/2003 | US6671221 Semiconductor chip with trimmable oscillator |
| 12/30/2003 | US6671214 Methods of operating a multiple bit line column redundancy scheme having primary and redundant local and global bit lines |
| 12/30/2003 | US6671213 Thin film magnetic memory device having redundancy repair function |
| 12/30/2003 | US6671204 Nonvolatile memory device with page buffer having dual registers and methods of using the same |
| 12/30/2003 | US6671203 Nonvolatile semiconductor memory having page mode with a plurality of banks |
| 12/30/2003 | US6671040 Programming methods and circuits for semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric |
| 12/30/2003 | US6670802 Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits |
| 12/30/2003 | CA2345570C Programmable circuit with preview function |
| 12/25/2003 | US20030237061 Test method for yielding a known good die |
| 12/25/2003 | US20030237036 Semiconductor integrated circuit with built-in self-test function and system including the same |
| 12/25/2003 | US20030237033 System for testing a group of functionally independent memories and for replacing failing memory words |
| 12/25/2003 | US20030237032 Method for electronically testing memory modules |
| 12/25/2003 | US20030237031 Memory module testing/repairing method and device |