| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 05/19/2004 | CN1497729A Integrated circuit self-testing method based on electric programmed three-D memory |
| 05/19/2004 | CN1150560C Semiconductor memory |
| 05/19/2004 | CN1150559C Circuit device for compensating different voltage on connection wire of integrated semiconductor circuit |
| 05/19/2004 | CN1150457C Memory address generator in convolutional interleaver/deinterleaver |
| 05/18/2004 | US6738938 Method for collecting failure information for a memory using an embedded test controller |
| 05/18/2004 | US6738937 Method for nondisruptive testing of device and host attachment to storage subsystems |
| 05/18/2004 | US6738882 Concurrent multi-processor memory testing beyond 32-bit addresses |
| 05/18/2004 | US6738299 Semiconductor memory device with redundant memory cells |
| 05/18/2004 | US6738298 Automatic reference voltage regulation in a memory device |
| 05/18/2004 | US6737906 Semiconductor integrated circuit device including a negative power supply circuit |
| 05/13/2004 | WO2004040769A1 Self-adjusting programmable on-chip clock aligner |
| 05/13/2004 | WO2004040586A1 Automated wear leveling in non-volatile storage systems |
| 05/13/2004 | US20040093555 Method and apparatus for managing data integrity of backup and disaster recovery data |
| 05/13/2004 | US20040093540 Two-dimensional redundancy calculation |
| 05/13/2004 | US20040093539 Method for testing embedded DRAM arrays |
| 05/13/2004 | US20040093478 Integrated circuit device and method for applying different types of signals to internal circuit via one pin |
| 05/13/2004 | US20040093472 Memory controllers with interleaved mirrored memory modes |
| 05/13/2004 | US20040093388 Test validation of an integrated device |
| 05/13/2004 | US20040093361 Method and apparatus for storage system to provide distributed data storage and protection |
| 05/13/2004 | US20040090920 Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application |
| 05/13/2004 | US20040090853 Integrated dynamic memory and operating method |
| 05/13/2004 | US20040090851 Nonvolatile semiconductor memory having page mode with a plurality of banks |
| 05/13/2004 | US20040090848 DIMM and method for producing a DIMM |
| 05/13/2004 | US20040090847 Non-volatile semiconductor memory |
| 05/13/2004 | US20040090837 Semiconductor memory device and test method of the same |
| 05/13/2004 | US20040090835 Magentic memory and method for optimizing write current a in magnetic memory |
| 05/13/2004 | US20040090831 Dedicated redundancy circuits for different operations in a flash memory device and methods of operating the same |
| 05/13/2004 | US20040090821 Multi-mode synchronous memory device and methods of operating and testing same |
| 05/13/2004 | US20040090814 Semiconductor memory device |
| 05/13/2004 | US20040090810 Ferroelectric memory |
| 05/13/2004 | DE10248753A1 Halbleiterbaustein sowie Verfahren zum Funktionstest und zur Konfiguration eines Halbleiterbausteins Semiconductor device and method for functional testing and configuration of a semiconductor device |
| 05/13/2004 | CA2503731A1 Self-adjusting programmable on-chip clock aligner |
| 05/12/2004 | EP1418502A2 Unusable block management within a non-volatile memory system |
| 05/12/2004 | EP1417502A2 Electronic circuit and method for testing |
| 05/12/2004 | CN1495992A circuit for on-off reluctance motor |
| 05/12/2004 | CN1495799A Special-purpose redundant circuit for different operations in internal memory device and its operation method |
| 05/12/2004 | CN1495797A Semiconductor storage equipment with storage unit array which is divided into block |
| 05/12/2004 | CN1495796A Semiconductor storage and its testing method |
| 05/12/2004 | CN1495794A Semiconductor storage device |
| 05/12/2004 | CN1495783A Optical disk recording/reproducing method, optical disk and optical disk equipment |
| 05/12/2004 | CN1495772A Information regenerative device |
| 05/12/2004 | CN1149656C Service signal generating circuit |
| 05/11/2004 | US6735729 Compression circuit for testing a memory device |
| 05/11/2004 | US6735727 Flash memory device with a novel redundancy selection circuit and method of using the same |
| 05/11/2004 | US6735726 Method of deciding error rate and semiconductor integrated circuit device |
| 05/11/2004 | US6735709 Method of timing calibration using slower data rate pattern |
| 05/11/2004 | US6735133 Semiconductor memory circuit having normal operation mode and burn-in test mode |
| 05/11/2004 | US6735132 6F2 DRAM array with apparatus for stress testing an isolation gate and method |
| 05/11/2004 | US6735131 Weak current generation |
| 05/11/2004 | US6735129 Semiconductor integrated circuit device |
| 05/11/2004 | US6735122 Method and architecture to calibrate read operations in synchronous flash memory |
| 05/11/2004 | US6735120 Semiconductor device having a high-speed data read operation |
| 05/11/2004 | US6735106 Accelerated fatigue testing |
| 05/11/2004 | US6735102 256 Meg dynamic random access memory |
| 05/11/2004 | US6734744 SRAM process monitor cell |
| 05/11/2004 | US6734743 Oscillation based cycle time measurement |
| 05/11/2004 | US6734693 Semiconductor integrated circuit having a semiconductor storage circuit and a test circuit for testing the semiconductor storage circuit |
| 05/11/2004 | US6734549 Semiconductor device having a device for testing the semiconductor |
| 05/06/2004 | WO2004038561A2 Reliable and secure updating and recovery of firmware from a mass storage device |
| 05/06/2004 | WO2004023239A3 Method of recovering overerased bits in a memory device |
| 05/06/2004 | WO2003098633A3 Content addressable memory (cam) with error checking and correction |
| 05/06/2004 | US20040088636 Error detection/correction code which detects and corrects a first failing component and optionally a second failing component |
| 05/06/2004 | US20040088621 Built-in self-test circuit |
| 05/06/2004 | US20040088614 Management system for defective memory |
| 05/06/2004 | US20040088612 Redundancy circuit of semiconductor memory device and fail repair method using the same |
| 05/06/2004 | US20040088603 Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache |
| 05/06/2004 | US20040088382 Method and apparatus for server share migration and server recovery using hierarchical storage management |
| 05/06/2004 | US20040088331 Method and apparatus for integrating primary data storage with local and remote data protection |
| 05/06/2004 | US20040088074 Auto classification shipping system |
| 05/06/2004 | US20040085845 Semiconductor device and semiconductor memory device provided with internal current setting adjustment circuit |
| 05/06/2004 | US20040085843 Auto-tuneable reference circuit for flash eeprom products |
| 05/06/2004 | US20040085838 Integrated circuit reset circuitry |
| 05/06/2004 | US20040085837 Mode entrance control circuit and mode entering method in semiconductor memory device |
| 05/06/2004 | US20040085836 Memory device in semiconductor for enhancing ability of test |
| 05/06/2004 | US20040085832 Semiconductor memory device and method of controlling the same |
| 05/06/2004 | US20040085827 Nonvolatile solid-state magnetic memory, method for controlling coercive force of nonvolatile solid-state magnetic memory, and method for recording in nonvolatile solid-state magnetic memory |
| 05/06/2004 | US20040085826 Semiconductor integrated circuit with memory redundancy circuit |
| 05/06/2004 | US20040085825 Content addressable memory device capable of reducing memory capacity |
| 05/06/2004 | US20040085821 Self-repairing built-in self test for linked list memories |
| 05/06/2004 | US20040085818 Methods and apparatus for improved memory access |
| 05/06/2004 | US20040085812 Method and apparatus for programming and testing a non-volatile memory cell for storing multibit states |
| 05/06/2004 | US20040085804 Synchronous controlled, self-timed local SRAM block |
| 05/06/2004 | US20040085799 Semiconductor memory device with memory cell array divided into blocks |
| 05/06/2004 | US20040085796 System-in-package type semiconductor device |
| 05/06/2004 | US20040085690 Semiconductor integrated circuit |
| 05/06/2004 | US20040085119 Method and circuit for controlling fuse blow |
| 05/06/2004 | US20040085084 Method and apparatus for stress testing integrated circuits using an adjustable AC hot carrier injection source |
| 05/06/2004 | US20040084158 Fabric light control window covering |
| 05/06/2004 | EP1416641A1 Method for compressing high repetitivity data, in particular data used in memory device testing |
| 05/06/2004 | EP1416499A1 Self-repairing built-in self test for linked list memories |
| 05/06/2004 | EP1415305A2 Duty-cycle-efficient sram cell test |
| 05/06/2004 | DE10224255B4 Speicherbaustein mit einer Speicherzellenanordnung und einer Teststruktur Memory device having a memory cell array and a test structure |
| 05/06/2004 | DE10135583B4 Datengenerator zur Erzeugung von Testdaten für wortorientierte Halbleiterspeicher Data generator for generating test data for word-oriented semiconductor memory |
| 05/05/2004 | CN1494145A Fuse element and integrated circuit device using said element |
| 05/05/2004 | CN1494085A Storage circuit with redundant structure |
| 05/05/2004 | CN1493988A Method for testing semiconductor integrated circuit and memory |
| 05/04/2004 | US6732322 Encoding method and memory device |
| 05/04/2004 | US6732308 Integration of embedded and test mode timer |
| 05/04/2004 | US6732306 Special programming mode with hashing |
| 05/04/2004 | US6732305 Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitry |