| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 06/03/2004 | US20040105338 Synchronous controlled, self-timed local SRAM block |
| 06/03/2004 | US20040105334 Semiconductor memory device having test mode |
| 06/03/2004 | US20040105327 Nonvolatile semiconductor storage device and row-line short defect detection method |
| 06/03/2004 | US20040105326 Magnetic semiconductor memory device |
| 06/03/2004 | US20040105318 Content addressable memory device that can be saved by reduction of memory capacity |
| 06/03/2004 | US20040105307 Writable tracking cells |
| 06/03/2004 | US20040105289 Method and apparatus for replacing defective rows in a semiconductor memory array |
| 06/03/2004 | US20040104752 System and method for expanding a pulse width |
| 06/03/2004 | DE10353371A1 Verfahren und Implementierung eines Selbstauffrischmerkmals auf einem Chip Procedures and implementation of a Selbstauffrischmerkmals on a chip |
| 06/03/2004 | DE10334821A1 Halbleiterspeicherschaltung mit normalem Betriebsmodus und Burn-in-Testmodus A semiconductor memory circuit having a normal operating mode and the burn-in test mode |
| 06/03/2004 | DE10254324A1 Electronic memory component has memory cell area, in which physical states are presented by function of representation that is presented by error correction code |
| 06/02/2004 | EP1424631A1 Hybrid implementation for error correction codes within a non-volatile memory system |
| 06/02/2004 | EP1273010B1 Method and apparatus for improving the testing, yield and performance of very large scale integrated circuits |
| 06/02/2004 | CN1502133A Programmable memory address and decode circuits with ultra thin vertical body transistors |
| 06/02/2004 | CN1502111A 增强的特殊编程模式 Enhanced special programming mode |
| 06/02/2004 | CN1502110A Special programming mode with external verification |
| 06/02/2004 | CN1501407A Semiconductor storing device |
| 06/02/2004 | CN1501404A Non volatile memory |
| 06/02/2004 | CN1501090A Scanning device of boundary |
| 06/02/2004 | CN1152431C Semiconductor integrated circuit with DRAM |
| 06/01/2004 | US6745370 Method for selecting an optimal level of redundancy in the design of memories |
| 06/01/2004 | US6745366 Error correcting method and apparatus for N:N+1 channel codes |
| 06/01/2004 | US6745261 Method for connecting caches in external storage subsystem |
| 06/01/2004 | US6744691 Semiconductor memory module |
| 06/01/2004 | US6744683 Semiconductor device removing disconnection defect in fuse element of its program circuit to stably perform coincidence comparison operation |
| 06/01/2004 | US6744682 Semiconductor memory with jointly usable fuses |
| 06/01/2004 | US6744681 Fault-tolerant solid state memory |
| 06/01/2004 | US6744665 Memory cell configuration |
| 06/01/2004 | US6744655 Method and apparatus for testing a CAM addressed cache |
| 06/01/2004 | US6744273 Semiconductor device capable of reducing noise to signal line |
| 06/01/2004 | US6744272 Test circuit |
| 06/01/2004 | US6744127 Semiconductor chip, memory module and method for testing the semiconductor chip |
| 06/01/2004 | US6743647 Semiconductor memory device manufacturing method |
| 05/27/2004 | WO2004044922A1 High speed vector access method from pattern memory for test systems |
| 05/27/2004 | WO2004044752A2 Memory controllers with interleaved mirrored memory modes |
| 05/27/2004 | WO2004029982A3 Acceleration of the programming of a memory module with the aid of a boundary scan (bscan) register |
| 05/27/2004 | WO2004017162A3 System and method for self-testing and repair of memory modules |
| 05/27/2004 | US20040103356 Modular test controller with BISTcircuit for testing embedded DRAM circuits |
| 05/27/2004 | US20040103352 Increasing possible test patterns which can be used with sequential scanning techniques to perform speed analysis |
| 05/27/2004 | US20040103346 Integrated circuit in a maximum input/output configuration |
| 05/27/2004 | US20040103255 Memory sub-array selection monitoring |
| 05/27/2004 | US20040103226 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with clock signal, and memory device and computer system using same |
| 05/27/2004 | US20040100840 Integrated circuit device with a built-in detecting circuit for detecting maximum memory access time of an embedded memory |
| 05/27/2004 | US20040100839 Circuits and methods for generating high frequency extended test pattern data from low frequency test pattern data input to an integrated circuit memory device |
| 05/27/2004 | US20040100833 Semiconductor memory enabling correct substitution of redundant cell array |
| 05/27/2004 | US20040100831 Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions |
| 05/27/2004 | US20040100827 Multibank memory on a die |
| 05/27/2004 | US20040100821 Enhanced fuse configurations for low-voltage flash memories |
| 05/27/2004 | US20040100336 Ring oscillator circuit for edram/dram performance monitoring |
| 05/27/2004 | US20040100246 Circuit configuration and method for measuring at least one operating parameter for an integrated circuit |
| 05/27/2004 | DE69724318T2 Prüfung und Reparatur einer eingebetteten Speicherschaltung Inspection and repair of an embedded memory circuit |
| 05/27/2004 | DE69333263T2 Nichtflüchtiger Halbleiterspeicher mit elektrisch und gemeinsam löschbaren Eigenschaften A non-volatile semiconductor memory having electrically and collectively erasable characteristics |
| 05/27/2004 | DE10321913A1 System-in-package-Halbleitervorrichtung System-in-package semiconductor device |
| 05/26/2004 | EP0686907B1 Memory system with hierarchic disk array and memory map store for persistent storage of virtual mapping information |
| 05/26/2004 | CN1499636A System combined semiconductor device |
| 05/26/2004 | CN1499599A Device and method for parallel testing semiconductor device |
| 05/26/2004 | CN1499533A Testing method of embedding DRAM array |
| 05/26/2004 | CN1499532A Hybrid realization of error correcting code in non-volatile memory |
| 05/26/2004 | CN1499516A Semiconductor memory having enhanced testing power |
| 05/26/2004 | CN1499212A Device for indicating capacity and method for measuring capacity |
| 05/26/2004 | CN1151439C Method and device for storage of reference information |
| 05/25/2004 | US6742159 Address parity error processing method, and apparatus and storage for the method |
| 05/25/2004 | US6742148 System and method for testing memory while an operating system is active |
| 05/25/2004 | US6742146 Techniques for providing data within a data storage system |
| 05/25/2004 | US6742144 Local heating of memory modules tested on a multi-motherboard tester |
| 05/25/2004 | US6742078 Management, data link structure and calculating method for flash memory |
| 05/25/2004 | US6741512 Integrated circuit memory devices having efficient multi-row address test capability and methods of operating same |
| 05/25/2004 | US6741511 Semiconductor memory device |
| 05/25/2004 | US6741510 Semiconductor memory device capable of performing burn-in test at high speed |
| 05/25/2004 | US6741509 Semiconductor storage device formed to optimize test technique and redundancy technology |
| 05/25/2004 | US6741499 Non-volatile semiconductor memory device |
| 05/25/2004 | US6741498 Non-volatile memory with common source |
| 05/25/2004 | US6741117 Antifuse circuit |
| 05/25/2004 | US6740979 Semiconductor device and LSI defect analyzing method using the same |
| 05/25/2004 | US6740929 Semiconductor device and method for testing semiconductor device |
| 05/21/2004 | WO2004042739A1 Method and apparatus for programming and testing a nonvolatile memory cell for storing multibit states |
| 05/21/2004 | WO2004042506A2 Methods and apparatus for improved memory access |
| 05/20/2004 | US20040098654 FIFO memory with ECC function |
| 05/20/2004 | US20040098650 High speed vector access method from pattern memory for test systems |
| 05/20/2004 | US20040098644 System and method for generating a graphical representation of fault data of a memory device under test |
| 05/20/2004 | US20040098643 Method and apparatus for accessing internal RAMs during diagnostic testing |
| 05/20/2004 | US20040098555 Method for dynamic memory management |
| 05/20/2004 | US20040097093 Test circuit for semiconductor device |
| 05/20/2004 | US20040095835 Circuits and methods for changing page length in a semiconductor memory device |
| 05/20/2004 | US20040095824 Semiconductor memory device |
| 05/20/2004 | US20040095822 Circuit and method for voltage regulation in a semiconductor device |
| 05/20/2004 | US20040095821 2T2C signal margin test mode using a defined charge exchange between BL and/BL |
| 05/20/2004 | US20040095820 2t2c signal margin test mode using resistive element |
| 05/20/2004 | US20040095819 2T2C Signal margin test mode using a defined charge and discharge of BL and /BL |
| 05/20/2004 | US20040095810 Automatic reference voltage regulation in a memory device |
| 05/20/2004 | US20040095800 Method and system for controlling an sram sense amplifier clock |
| 05/20/2004 | US20040095799 2T2C signal margin test mode using different pre-charge levels for BL and/BL |
| 05/20/2004 | US20040095172 Semiconductor device having identification number, manufacturing method thereof and electronic device |
| 05/20/2004 | US20040094778 Semiconductor device and semiconductor memory device provided with internal current setting adjustment circuit |
| 05/19/2004 | EP1419507A2 Method and device for testing semiconductor memory devices |
| 05/19/2004 | EP1292889B1 Secure eeprom comprising an error correction circuit |
| 05/19/2004 | DE10348870A1 Ein Verfahren und eine Schaltung zum Steuern des Durchbrennens von Schmelzelementen A method and a circuit for controlling the burning of fuse elements |
| 05/19/2004 | DE10252199A1 Method for writing to error address store e.g. for testing integrated memory circuits, requires assigning address in error address store to memory zone |
| 05/19/2004 | DE10231680B4 Integrierter Speicher Built-in Memory |
| 05/19/2004 | CN1498367A Information processing device, momery management device, memory management method and information processing method |