| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 07/15/2004 | US20040139282 Apparatus and method for memory management |
| 07/15/2004 | US20040138841 Method and apparatus for detecting an unused state in a semiconductor circuit |
| 07/15/2004 | US20040136257 Method and System For Merging Multiple Fuse Decompression Serial Bitstreams To Support Auxiliary Fuseblow Capability |
| 07/15/2004 | US20040136249 Circuit arrangement having a number of integrated circuit components on a carrier substrate and method for testing a circuit arrangement of this type |
| 07/15/2004 | US20040136248 Semiconductor memory |
| 07/15/2004 | US20040136230 Logic-merged memory |
| 07/15/2004 | US20040136220 Method circuit and system for determining a reference voltage |
| 07/15/2004 | US20040135616 Control signal generation circuit and method for generating control signal controlled in units of bit time |
| 07/15/2004 | US20040135177 Semiconductor integrated circuit having a scan test |
| 07/15/2004 | DE60006031T2 Speicherfehlerkorrektur mit einem redundanten geschnittenen Speicher und Standard ECC Mechanismus Memory error correction with a redundant-cut standard ECC memory and mechanism |
| 07/15/2004 | DE19581814B4 Halbleiter-Testchip mit waferintegrierter Schaltmatrix Semiconductor wafer test chip with integrated switching matrix |
| 07/15/2004 | DE10344021A1 Non-volatile memory device e.g. NAND-type flash memory, has memory cell array and gating circuit connected by page buffer whose main and auxiliary registers are controlled by operation of transistor |
| 07/15/2004 | DE10260184A1 Memory module with in-built tester with electronic circuit board carrying numerous components with tester of electric functioning of components fitted on circuit board separately from memory components such that it generates control signal |
| 07/15/2004 | DE10259300A1 Stacked memory module testing method, in which different values are written to a memory cell in memory chips in same stack and simultaneously values derived from test signals are applied to a pin of each chip |
| 07/15/2004 | DE10258199A1 Schaltungsanordnung mit einer Anzahl von integrierten Schaltungsbauelementen auf einem Trägersubstrat und Verfahren zum Test einer derartigen Schaltungsanordnung Circuit arrangement having a number of integrated circuit components on a carrier substrate and method for testing such a circuit arrangement |
| 07/15/2004 | DE10233910B4 Schaltungsanordnung zum Auslesen einer programmierbaren Verbindung Circuitry for reading a programmable interconnect |
| 07/14/2004 | EP1436815A1 Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric |
| 07/14/2004 | EP1040358B1 A memory test system with a means for test sequence optimisation and a method of its operation |
| 07/14/2004 | CN2626013Y Circuit for testing EEPROM |
| 07/14/2004 | CN1512511A Management of unusable block in non-volatile memory system |
| 07/14/2004 | CN1512510A Fault removing circuit for storage |
| 07/14/2004 | CN1512348A Device and method for storage management |
| 07/14/2004 | CN1157791C Semiconductor storage device and method for fetch said device in test pattern |
| 07/14/2004 | CN1157739C Memory test set |
| 07/14/2004 | CN1157736C Circuit for generating reference voltage for reading out from ferroelectric memory |
| 07/13/2004 | US6763490 Method and apparatus for coordinating program execution in a site controller with pattern execution in a tester |
| 07/13/2004 | US6763480 Flash EEprom system |
| 07/13/2004 | US6763444 Read/write timing calibration of a memory array using a row or a redundant row |
| 07/13/2004 | US6763398 Modular RAID controller |
| 07/13/2004 | US6763079 Semiconductor device allowing easy confirmation of operation of built in clock generation circuit |
| 07/13/2004 | US6762971 Semiconductor memory device |
| 07/13/2004 | US6762969 Semiconductor integrated circuit and method of manufacturing of semiconductor integrated circuit |
| 07/13/2004 | US6762967 Semiconductor memory device having a circuit for fast operation |
| 07/13/2004 | US6762966 Method and circuit to investigate charge transfer array transistor characteristics and aging under realistic stress and its implementation to DRAM MOSFET array transistor |
| 07/13/2004 | US6762965 Method for integrating imperfect semiconductor memory devices in data processing apparatus |
| 07/13/2004 | US6762964 Semiconductor device with flexible redundancy system |
| 07/13/2004 | US6762963 Semiconductor memory having dynamic memory cells and a redundancy relief circuit |
| 07/13/2004 | US6762954 Local probe of magnetic properties |
| 07/13/2004 | US6762949 Dynamic RAM-and semiconductor device |
| 07/13/2004 | US6762948 Semiconductor memory device having first and second memory architecture and memory system using the same |
| 07/13/2004 | US6762617 Semiconductor device having test mode entry circuit |
| 07/13/2004 | US6762615 Parallel test board used in testing semiconductor memory devices |
| 07/13/2004 | US6762614 Systems and methods for facilitating driver strength testing of integrated circuits |
| 07/13/2004 | US6762611 Test configuration and test method for testing a plurality of integrated circuits in parallel |
| 07/13/2004 | US6762599 Semiconductor integrated circuit tester |
| 07/08/2004 | WO2004057354A1 Semiconductor test instrument |
| 07/08/2004 | WO2004025664A3 Signal margin test circuit of a memory |
| 07/08/2004 | US20040133838 Method for recovering data in portable information device, portable information device, and computer product |
| 07/08/2004 | US20040133830 Semiconductor device with speed binning test circuit and test method thereof |
| 07/08/2004 | US20040133828 Compression circuit for testing a momory device |
| 07/08/2004 | US20040133827 Internal data generation and compare via unused external pins |
| 07/08/2004 | US20040133826 Memory redundancy with programmable non-volatile control |
| 07/08/2004 | US20040132303 Membrane 3D IC fabrication |
| 07/08/2004 | US20040132250 Preventing dielectric thickening over a gate area of a transistor |
| 07/08/2004 | US20040130957 Method and circuit to investigate charge transfer array transistor characteristics and aging under realistic stress and its implementation to dram mosfet array transistor |
| 07/08/2004 | US20040130954 Data transfer unit and method |
| 07/08/2004 | US20040130953 Nonvolatile storage device and self-redundancy method for the same |
| 07/08/2004 | US20040130952 Circuit and method for transforming data input/output format in parallel bit test |
| 07/08/2004 | US20040130944 Programming flash memory via a boundary scan register |
| 07/08/2004 | US20040130344 Systems and methods for testing receiver terminations in integrated circuits |
| 07/08/2004 | US20040129952 Integrated circuit with programmable fuse array |
| 07/08/2004 | DE19604764B4 Halbleiterspeichereinrichtung und Verfahren zum Auswählen einer Wortleitung in einer Halbleiterspeichereinrichtung A semiconductor memory device and method for selecting a word line in a semiconductor memory device |
| 07/08/2004 | DE10343563A1 Flashspeicher mit Wortleitungs-Reparaturmöglichkeit Flash memory with word-Repair |
| 07/08/2004 | DE10256487A1 Integrated memory circuit with several memory cells, has self-testing unit and redundancy analysis memory and computer unit to detect defective memory cells so that they can be replaced by redundant cells |
| 07/08/2004 | DE10137345B4 Schaltungsvorrichtung zur Prüfung zumindest eines von einer integrierten Schaltung ausgegebenen Prüfsignals, eine Anordnung eines Testsystems für integierte Schaltungen, eine Verwendung der Anordnung sowie ein Verfahren zur Prüfung zumindest eines Prüfsignals Circuit device for testing at least one test signal output from an integrated circuit, an arrangement of a test system for integierte circuits, a use of the arrangement as well as a method for testing at least one test signal |
| 07/08/2004 | DE10131388B4 Integrierter dynamischer Speicher und Verfahren zum Betrieb desselben Of the same integrated dynamic memory and method of operating |
| 07/08/2004 | DE10123154B4 Halbleitervorrichtungs-Prüfvorrichtung und Verfahren zum Prüfen einer Halbleitervorrichtung The semiconductor device testing apparatus and method for testing a semiconductor device |
| 07/07/2004 | EP1435625A1 Non volatile memory device including a predetermined number of sectors |
| 07/07/2004 | EP1435574A2 A structure and method for detecting errors in a multilevel memory device with improved programming granularity |
| 07/07/2004 | EP0805460B1 Integrated circuit having a built-in selft-test arrangement |
| 07/07/2004 | CN1511323A Dynamic memory and method for testing dynamic memory |
| 07/07/2004 | CN1511263A Apparatus and method for testing circuit modules |
| 07/07/2004 | CN1510752A Semiconductor device with redundant function |
| 07/07/2004 | CN1510751A Semiconductor devices |
| 07/07/2004 | CN1156854C Method for functionally testing memory cells of integrated semiconductor memory |
| 07/06/2004 | US6760872 Configurable and memory architecture independent memory built-in self test |
| 07/06/2004 | US6760871 Circuit, system and method for arranging data output by semiconductor testers to packet-based devices under test |
| 07/06/2004 | US6760865 Multiple level built-in self-test controller and method therefor |
| 07/06/2004 | US6760857 System having both externally and internally generated clock signals being asserted on the same clock pin in normal and test modes of operation respectively |
| 07/06/2004 | US6760814 Methods and apparatus for loading CRC values into a CRC cache in a storage controller |
| 07/06/2004 | US6760243 Distributed, highly configurable modular predecoding |
| 07/06/2004 | US6759895 Data latch circuit having anti-fuse elements |
| 07/06/2004 | US6759894 Method and circuit for controlling fuse blow |
| 07/06/2004 | US6759871 Line segmentation in programmable logic devices having redundancy circuitry |
| 07/06/2004 | US6759866 Semiconductor integrated circuit and a testing method thereof |
| 07/06/2004 | US6759257 Structure and method for embedding capacitors in z-connected multi-chip modules |
| 07/01/2004 | WO2004055830A1 Error recovery for nonvolatile memory |
| 07/01/2004 | WO2004055829A1 Method and circuit for real time collecting memory failure information |
| 07/01/2004 | WO2004027615A3 Method of and apparatus for detecting an error in writing to persistent memory |
| 07/01/2004 | US20040128635 Semiconductor integrated circuit device |
| 07/01/2004 | US20040128604 Memory bypass with support for path delay test |
| 07/01/2004 | US20040128601 Arrangements for self-measurement of I/O specifications |
| 07/01/2004 | US20040128600 Built-in self-test hierarchy for an integrated circuit |
| 07/01/2004 | US20040128598 Integrated circuit device including a scan test circuit and methods of testing the same |
| 07/01/2004 | US20040128596 Method and apparatus for testing embedded cores |
| 07/01/2004 | US20040128594 High bandwidth datapath load and test of multi-level memory cells |
| 07/01/2004 | US20040128593 Fault repair controller for redundant memory integrated circuits |
| 07/01/2004 | US20040128429 Method of addressing individual memory devices on a memory module |
| 07/01/2004 | US20040128406 Test sequences generated by automatic test pattern generation and applicable to circuits with embedded multi-port RAMs |
| 07/01/2004 | US20040128115 Hierarchical power supply noise monitoring device and system for very large scale integrated circuits |