| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 08/31/2004 | US6785629 Accuracy determination in bit line voltage measurements |
| 08/31/2004 | US6785187 Semiconductor device having integrated memory and logic |
| 08/31/2004 | US6785181 Semiconductor memory device and electronic instrument |
| 08/31/2004 | US6785175 Method for repairing memory cell |
| 08/31/2004 | US6785174 Testing method and device for non-volatile memories having a LPC (low pin count) communication serial interface |
| 08/31/2004 | US6785173 Semiconductor memory device capable of performing high-frequency wafer test operation |
| 08/31/2004 | US6785172 Semiconductor memory device |
| 08/31/2004 | US6785171 Semiconductor memory device |
| 08/31/2004 | US6785170 Data memory with short memory access time |
| 08/31/2004 | US6785162 Test mode decoder in a flash memory |
| 08/31/2004 | US6785143 Semiconductor memory module |
| 08/31/2004 | US6784704 Semiconductor integrated circuit having circuit for changing timing of inactivating power-on resetting circuit |
| 08/31/2004 | US6784683 Circuit configuration for selectively transmitting information items from a measuring device to chips on a wafer during chip fabrication |
| 08/31/2004 | US6784668 Electrical conduction array on the bottom side of a tester thermal head |
| 08/31/2004 | US6784043 Methods for forming aligned fuses disposed in an integrated circuit |
| 08/26/2004 | WO2004073041A2 Testing embedded memories in an integrated circuit |
| 08/26/2004 | WO2004072983A1 Semiconductor device and method for controlling semiconductor device |
| 08/26/2004 | WO2004072660A2 Compressing test responses using a compactor |
| 08/26/2004 | WO2004047116A8 2t2c signal margin test mode using different pre-charge levels for bl and /bl |
| 08/26/2004 | WO2004047115A8 2t2c signal margin test mode using a defined charge exchange between bl and /bl |
| 08/26/2004 | US20040168102 Apparatus and method for verifying erasure correction function |
| 08/26/2004 | US20040168017 Method of writing, erasing, and controlling memory for memory device |
| 08/26/2004 | US20040168013 Method of writing, erasing, and controlling memory for memory device |
| 08/26/2004 | US20040165472 Pseudo-static synchronous semiconductor memory device |
| 08/26/2004 | US20040165469 Semiconductor memory device and method for selecting multiple word lines in a semiconductor memory device |
| 08/26/2004 | US20040165467 Semiconductor integrated circuit and method of manufacturing of semiconductor integrated circuit |
| 08/26/2004 | US20040165457 Integrated circuit having a non-volatile memory cell transistor as a fuse device |
| 08/26/2004 | US20040165456 Semiconductor memory having a defective memory cell relieving circuit |
| 08/26/2004 | US20040165452 Semiconductor memory device including RAS guarantee circuit |
| 08/26/2004 | US20040165451 Semiconductor memory device |
| 08/26/2004 | US20040165445 Semiconductor nonvolatile storage device |
| 08/26/2004 | US20040165444 Method and architecture to calibrate read operations in synchronous flash memory |
| 08/26/2004 | US20040165441 Flash array implementation with local and global bit lines |
| 08/26/2004 | US20040165440 Flash array implementation with local and global bit lines |
| 08/26/2004 | US20040165439 Flash array implementation with local and global bit lines |
| 08/26/2004 | US20040165438 Flash array implementation with local and global bit lines |
| 08/26/2004 | US20040165437 Flash array implementation with local and global bit lines |
| 08/26/2004 | US20040165436 Flash array implementation with local and global bit lines |
| 08/26/2004 | US20040165435 Flash array implementation with local and global bit lines |
| 08/26/2004 | US20040165419 Magnetic memory device with reference cell for data reading |
| 08/26/2004 | US20040165415 Method and system of testing data retention of memory |
| 08/26/2004 | US20040165410 Flash array implementation with local and global bit lines |
| 08/26/2004 | US20040165409 Flash array implementation with local and global bit lines |
| 08/26/2004 | US20040165071 Boundary scan device |
| 08/25/2004 | EP1450259A2 Flash memory |
| 08/25/2004 | EP1199726B1 Method and apparatus for testing integrated circuits |
| 08/25/2004 | EP1158530B1 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics |
| 08/25/2004 | CN1523367A Method for testing the performance and fault of EPROM |
| 08/25/2004 | CN1523364A Online testing method for field programmable gate array assembly on circuit board and circuit board |
| 08/25/2004 | CN1163908C Non-volatile semiconductor memory |
| 08/24/2004 | US6782499 Semiconductor integrated circuit device, method of manufacturing the device, and computer readable medium |
| 08/24/2004 | US6782498 Semiconductor memory device allowing mounting of built-in self test circuit without addition of interface specification |
| 08/24/2004 | US6782467 Method and apparatus for fast limited core area access and cross-port word size multiplication in synchronous multiport memories |
| 08/24/2004 | US6781916 Integrated volatile and non-volatile memory |
| 08/24/2004 | US6781908 Memory having variable refresh control and method therefor |
| 08/24/2004 | US6781902 Semiconductor memory device and method of testing short circuits between word lines and bit lines |
| 08/24/2004 | US6781901 Sacrifice read test mode |
| 08/24/2004 | US6781900 Semiconductor memory device with enhanced reliability |
| 08/24/2004 | US6781899 Semiconductor memory device and test method therof |
| 08/24/2004 | US6781898 Self-repairing built-in self test for linked list memories |
| 08/24/2004 | US6781897 Defects detection |
| 08/24/2004 | US6781896 MRAM semiconductor memory configuration with redundant cell arrays |
| 08/24/2004 | US6781895 Non-volatile semiconductor memory device and memory system using the same |
| 08/24/2004 | US6781889 Method for operating a semiconductor memory and semiconductor memory |
| 08/24/2004 | US6781883 Apparatus and method for margin testing single polysilicon EEPROM cells |
| 08/24/2004 | US6781879 Nonvolatile semiconductor memory with a page mode |
| 08/24/2004 | US6781878 Dynamic sub-array group selection scheme |
| 08/24/2004 | US6781862 Semiconductor memory device |
| 08/24/2004 | US6781398 Circuit for testing an integrated circuit |
| 08/24/2004 | US6781363 Memory sorting method and apparatus |
| 08/19/2004 | WO2004070727A2 Improved method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array |
| 08/19/2004 | WO2004070404A1 Test device |
| 08/19/2004 | WO2004047117A8 2t2c signal margin test mode using a defined charge and discharge of bl and /bl |
| 08/19/2004 | WO2002065291A3 Device for reconfiguring a faulty storage assembly |
| 08/19/2004 | US20040163066 Low voltage swing bus analysis method using static timing analysis tool |
| 08/19/2004 | US20040163029 Data recovery techniques in storage systems |
| 08/19/2004 | US20040163028 Technique for implementing chipkill in a memory system |
| 08/19/2004 | US20040163027 Technique for implementing chipkill in a memory system with X8 memory devices |
| 08/19/2004 | US20040163015 Memory repair analysis method and circuit |
| 08/19/2004 | US20040162959 Device identification using a memory profile |
| 08/19/2004 | US20040160853 Semiconductor memory device inputting/outputting data and parity data in burst operation |
| 08/19/2004 | US20040160838 Memory having variable refresh control and method therefor |
| 08/19/2004 | US20040160836 Semiconductor device with flexible redundancy system |
| 08/19/2004 | US20040160827 Nonvolatile semiconductor memory device and method of retrieving faulty in the same |
| 08/19/2004 | US20040160826 Memory with row redundancy |
| 08/19/2004 | US20040160243 System, method and apparatus for improving sense amplifier performance characteristics using process feedback |
| 08/19/2004 | DE10303963A1 Integrated electronic circuit having vertical FET devices in an array in a structure having deep channels |
| 08/19/2004 | DE10106557B4 Testanordnung zum parallelen Hochfrequenztest einer Mehrzahl von Halbleiterbausteinen Test arrangement for parallel high-frequency test a plurality of semiconductor devices |
| 08/18/2004 | EP1447814A1 Method and apparatus for testing embedded memory on devices with multiple processor cores |
| 08/18/2004 | EP1447813A1 Memory built-in self repair (MBISR) circuits / devices and method for repairing a memory comprising a memory built-in self repair (MBISR) structure |
| 08/18/2004 | EP1065594B1 Error detection and correction circuit in a flash memory |
| 08/18/2004 | CN1521760A Film magnetic memory device of programmed element |
| 08/18/2004 | CN1162866C Semiconductor memory |
| 08/17/2004 | US6779150 CRC error detection system and method |
| 08/17/2004 | US6779144 Semiconductor integrated circuit device and method of testing it |
| 08/17/2004 | US6779141 System and method for implementing memory testing in a SRAM unit |
| 08/17/2004 | US6779140 Algorithmically programmable memory tester with test sites operating in a slave mode |
| 08/17/2004 | US6779139 Circuit for reducing test time and semiconductor memory device including the circuit |
| 08/17/2004 | US6779136 Method for testing the refresh device of an information memory |
| 08/17/2004 | US6779131 Reconfigurable multi-chip modules |