G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation

Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
11/2004
11/18/2004	US20040230884 Compressing test responses using a compactor
11/18/2004	US20040230880 Memory-Module Burn-In System With Removable Pattern-Generator Boards Separated from Heat Chamber by Backplane
11/18/2004	US20040230879 Apparatus and method for responding to data retention loss in a non-volatile memory unit using error checking and correction techniques
11/18/2004	US20040230870 Built-in self test system and method
11/18/2004	US20040230395 Universally accessible fully programmable memory built-in self-test (MBIST) system and method
11/18/2004	US20040228198 Semiconductor memory device including reference memory cell and control method
11/18/2004	US20040228191 Circuit and method for fuse disposing in a semiconductor memory device
11/18/2004	US20040228182 Semiconductor memory device for improving redundancy efficiency
11/18/2004	US20040227562 Fuse detection circuit
11/18/2004	US20040227166 Reference current generator, and method of programming, adjusting and/or operating same
11/18/2004	DE69825234T2 Verfahren und vorrichtung zur selbstprüfung von multi-port-rams Method and device for self-testing of multi-port rams
11/18/2004	DE10361692A1 Speichervorrichtung mit Testmodus zum Steuern einer Bitleitungs-Erfassungsspannenzeit Storage device with test mode for controlling a bit line sense span of time
11/18/2004	DE10361662A1 Semiconductor memory device, has repair circuit controller in response to delayed control signal for generating one of repair address and normal address enable signals based on comparison of address with stored repair address
11/18/2004	DE10359234A1 Mehrport-Speicher-Prüfverfahren unter Verwendung eines Sequenzfaltungsschemas zum Reduzieren der Prüfzeit Multiport memory test method using a sequence convolution scheme for reducing the test time
11/17/2004	EP1476880A2 Non-volatile redundancy addresses memory
11/17/2004	EP1476873A2 Removable memory media with integral indicator light
11/17/2004	EP0689125B1 Method of utilizing storage disks of differing capacity in a single storage volume in a hierarchic disk array
11/17/2004	CN1547215A ROM circuit capable of debugging and updating and method of debugging and updating
11/17/2004	CN1547210A Method and apparatus for picking absolute time data of prerecording ditch groove
11/16/2004	US6820244 Methods for testing and programming nanoscale electronic devices
11/16/2004	US6820224 Method and system for increasing yield in embedded memory devices
11/16/2004	US6819788 Failure analysis method that allows high-precision failure mode classification
11/16/2004	US6819611 Method and apparatus for data compression in memory devices
11/16/2004	US6819609 Semiconductor memory device with built-in self-diagnostic function and semiconductor device having the semiconductor memory device
11/16/2004	US6819608 Method of recovering memory module, memory module and volatile memory
11/16/2004	US6819607 Semiconductor memory device
11/16/2004	US6819606 Method for storing data in a memory device with the possibility of access to redundant memory cells
11/16/2004	US6819605 Semiconductor memory device and redundancy judging method
11/16/2004	US6819604 Semiconductor memory having a defective memory cell relieving circuit
11/16/2004	US6819597 Row decoder in flash memory and erase method of flash memory cell using the same
11/16/2004	US6819596 Semiconductor memory device with test mode
11/16/2004	US6819134 Decoding circuit for wafer burn-in test
11/16/2004	US6819129 Method and apparatus for testing a non-standard memory device under actual operating conditions
11/16/2004	US6818957 Semiconductor chip with fuse unit
11/11/2004	WO2004097842A1 Memory bit line leakage repair
11/11/2004	WO2004097841A1 Flash memory having a spare sector of reduced access time
11/11/2004	WO2004097840A1 Apparatus and method for generating test patterns for sdram
11/11/2004	WO2004097727A1 Memory card
11/11/2004	WO2004074851A3 Memory repair analysis method and circuit
11/11/2004	US20040225947 Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data
11/11/2004	US20040225939 Built-in self test system and method for two-dimensional memory redundancy allocation
11/11/2004	US20040225937 Testing of integrated circuit devices
11/11/2004	US20040225935 System and method for testing memory at full bandwidth
11/11/2004	US20040225934 Automatic test entry termination in a memory device
11/11/2004	US20040225912 Memory built-in self repair (MBISR) circuits/devices and method for repairing a memory comprising a memory built-in self repair (MBISR) structure
11/11/2004	US20040225841 Method and apparatus for providing full accessibility to instruction cache and microcode ROM
11/11/2004	US20040225825 Scratch control memory array in a flash memory device
11/11/2004	US20040223399 Method for detecting a resistive path or a predetermined potential in non-volatile memory electronic devices
11/11/2004	US20040223387 Method and test device for determining a repair solution for a memory module
11/11/2004	US20040223384 Semiconductor memory device and test method thereof
11/11/2004	US20040223370 Methods and circuits for programming of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric
11/11/2004	US20040223358 Semiconductor test apparatus
11/11/2004	US20040222812 Integrated circuit having a test circuit
11/11/2004	US20040222809 System for probing, testing, burn-in, repairing and programming of integrated circuits
11/11/2004	DE10317371A1 Data interface circuit for data exchange between integrated circuit and external circuit with data protocol unit preparing exchangeable data, with test data buffer, transmitting stored data in test mode to protocol unit
11/11/2004	DE10140853B4 Verfahren zum Hochvolt-Screening einer integrierten Schaltung A method for screening a high-voltage integrated circuit
11/10/2004	EP1206775B1 Flash memory device with externally triggered detection and repair of leaky cells
11/10/2004	CN1545708A Method and device for testing semiconductor memory devices
11/10/2004	CN1175425C Integrated memory with storage and reference unit
11/09/2004	US6816991 Built-in self-testing for double data rate input/output
11/09/2004	US6816986 Remapping memory devices during operation
11/09/2004	US6816429 Integrated circuit capable of being burn-in tested using an alternating current stress and a testing method using the same
11/09/2004	US6816426 Semiconductor device with self refresh test mode
11/09/2004	US6816422 Semiconductor memory device having multi-bit testing function
11/09/2004	US6816421 Nonvolatile semiconductor memory
11/09/2004	US6816420 Column redundancy scheme for serially programmable integrated circuits
11/09/2004	US6816419 Semiconductor device having a redundant memory cell and method for recovering the same
11/09/2004	US6816418 MIS semiconductor device having improved gate insulating film reliability
11/09/2004	US6816400 Circuit and method for testing a ferroelectric memory device
11/09/2004	US6815992 Circuit for testing and fine tuning integrated circuit (switch control circuit)
11/09/2004	US6815971 Method and apparatus for stress testing integrated circuits using an adjustable AC hot carrier injection source
11/09/2004	US6815658 Testing circuit for charge detection circuit, LSI, image sensor, and testing method for the charge detection circuit
11/09/2004	US6815231 Method of testing and manufacturing nonvolatile semiconductor memory
11/04/2004	WO2004095472A1 Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage
11/04/2004	WO2004095471A1 Semiconductor memory
11/04/2004	WO2004095461A2 Redundant memory structure using bad bit pointers
11/04/2004	WO2004070727A3 Improved method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array
11/04/2004	US20040221211 Individually adjustable back-bias technique
11/04/2004	US20040221210 Method and apparatus for masking known fails during memory tests readouts
11/04/2004	US20040221192 Method and system for minimizing the length of a defect list for a storage device
11/04/2004	US20040221188 Apparatus and method for providing a clock signal for testing
11/04/2004	US20040221109 Multi-port memory testing method utilizing a sequence folding scheme for testing time reduction
11/04/2004	US20040221098 Semiconductor integrated circuit device
11/04/2004	US20040219745 Memory device for reducing skew of data and address
11/04/2004	US20040218459 Oscillation based access time measurement
11/04/2004	US20040218454 Method and apparatus for implementing dram redundancy fuse latches using sram
11/04/2004	US20040218448 Semiconductor integrated circuit device, method of manufacturing the device, and computer readable medium
11/04/2004	US20040218441 Semiconductor memory having mutually crossing word and bit lines, at which magnetoresistive memory cells are arranged
11/04/2004	US20040218440 Built-in testing methodology in flash memory
11/04/2004	US20040218438 Memory device with test mode for controlling of bitline sensing margin time
11/04/2004	US20040218433 Semiconductor memory device having advanced repair circuit
11/04/2004	US20040218432 Semiconductor memory device with enhanced repair efficiency
11/04/2004	US20040218431 Semiconductor memory device and method of operating the same
11/04/2004	US20040218430 Semiconductor memory device with configurable on-chip delay circuit
11/04/2004	US20040218328 Fuse latch circuit
11/04/2004	US20040217386 Semiconductor device capable of adjusting operation timing using antifuse
11/04/2004	DE10316931A1 DRAM memory cell test method for mobile telephone or notebook computer, by performing self-test during time when memory cells are not accessed, and while device is operative
11/04/2004	DE10223178B4 Schaltungsanordnung mit einer Ablaufsteuerung, integrierter Speicher sowie Testanordnung mit einer derartigen Schaltungsanordnung Circuitry with a sequence control, integrated memory and test arrangement with such a circuit arrangement
11/04/2004	DE102004014451A1 Verfahren zum Messen der Verzögerungszeit einer Signalleitung A method of measuring the delay time of a signal line
11/04/2004	DE10140757B4 Verfahren zur Ermittlung der Laufzeit elektrischer Signale auf gedruckten Leiterplatten durch eine automatische Standardtestausrüstung A method for determining the transit time of electrical signals on printed circuit boards by automatic test equipment Standard

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