G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation

Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
12/2004
12/23/2004	DE10323865A1 Integrierte Schaltung, insbesondere integrierter Speicher, sowie Verfahren zum Betrieb einer integrierten Schaltung Integrated circuit, particularly an integrated memory, and method for operating an integrated circuit
12/23/2004	DE10323413A1 Test method for testing high-speed semiconductor memory, especially DDR-DRAM in conjunction with a memory control unit, whereby the test signal is provided by the memory control unit or a unit derived from it
12/23/2004	DE102004025977A1 Flash-Speicherbaustein Flash memory device
12/23/2004	DE102004002901A1 Verfahren zur Fehleranalyse einer Halbleiterbaugruppe Method for fault analysis of a semiconductor package
12/22/2004	EP1488424A2 Semiconductor memory device and method for initializing the same
12/22/2004	EP1214713A4 Architecture, method(s) and circuitry for low power memories
12/22/2004	EP1131718B1 Levelizing transfer delays for a channel of memory devices in a memory subsystem
12/21/2004	US6834368 Semiconductor integrated circuit including a test facilitation circuit for functional blocks intellectual properties and automatic insertion method of the same test facilitation circuit
12/21/2004	US6834366 Method of outputting internal information through test pin of semiconductor memory and output circuit thereof
12/21/2004	US6834364 Algorithmically programmable memory tester with breakpoint trigger, error jamming and 'scope mode that memorizes target sequences
12/21/2004	US6834361 Method of testing embedded memory array and embedded memory controller for use therewith
12/21/2004	US6834323 Method and apparatus including special programming mode circuitry which disables internal program verification operations by a memory
12/21/2004	US6834017 Error detection system for an information storage device
12/21/2004	US6834016 Semiconductor memory device having redundancy system
12/21/2004	US6833724 Methods and apparatus for testing electronic circuits
12/21/2004	US6833723 Semiconductor device with phase comparator comparing phases between internal signal and external signal
12/21/2004	US6833721 Method and apparatus for testing semiconductor devices using an actual board-type product
12/21/2004	US6833715 Semiconductor testing apparatus and semiconductor testing method
12/16/2004	WO2004109751A2 Fault tolerant data storage circuit
12/16/2004	WO2004109711A1 Semiconductor memory having booster circuit for redundant memory
12/16/2004	WO2004109710A1 Virtual grounding type non-volatile memory enabling test depending on adjacent cell state
12/16/2004	WO2004109706A2 Nanoscale wire-based sublithographic programmable logic arrays
12/16/2004	WO2004109704A1 Integrity control for data stored in a non-volatile memory
12/16/2004	WO2004109703A1 Deterministic addressing of nanoscale devices assembled at sublithographic pitches
12/16/2004	US20040255225 Control circuit for error checking and correction and memory controller
12/16/2004	US20040255224 Semiconductor storage device and evaluation method
12/16/2004	US20040255223 Method for storage array error correction
12/16/2004	US20040255212 Scan stream sequencing for testing integrated circuits
12/16/2004	US20040255211 Apparatus and method for reducing test resources in testing DRAMs
12/16/2004	US20040255210 Systems and methods for enhanced stored data verification utilizing pageable pool memory
12/16/2004	US20040255209 Apparatus and method for compressing redundancy information for embedded memories, including cache memories, of integrated circuits
12/16/2004	US20040255197 Multi-staged bios-based memory testing
12/16/2004	US20040255196 Fault tolerant data storage circuit
12/16/2004	US20040255089 Semiconductor memory device
12/16/2004	US20040252564 Test mode flag signal generator of semiconductor memory device
12/16/2004	US20040252552 Nonvolatile semiconductor memory with a page mode
12/16/2004	US20040252549 Systems and methods for simultaneously testing semiconductor memory devices
12/16/2004	US20040252540 Method and apparatus for assessing one-time programmable cells
12/16/2004	US20040251914 Test apparatus
12/16/2004	DE69821426T2 Speicheranordung, und Datenverarbeitungssystem und -Verfahren Speicheranordung, and data processing system and method
12/16/2004	DE69133365T2 Halbleiterspeicher mit sequenzgetakteten Zugriffscodes zum Eintritt in den Prüfmodus Semiconductor memory with sequence clocked access code to enter the test mode
12/16/2004	DE10323237A1 Modifying time period between execution operations in DRAM, by changing set time period in direction of real time period selected during test mode
12/16/2004	DE10322541A1 Memory chip with integral address scrambling unit whereby the address can be scrambled in different ways according to the address control bits
12/15/2004	EP1486983A1 Magnetic storage device using ferromagnetic tunnel junction element
12/15/2004	EP1485885A2 Smart card and method for avoiding software bug on such a smart card
12/15/2004	EP1216477A4 Circuit and method for column redundancy for high bandwidth memories
12/15/2004	CN1555341A Silicon plate, method for producing silicon plate and solar cell
12/15/2004	CN1555061A Error corrector
12/14/2004	US6832348 Semiconductor integrated circuit having self-diagnosis test function and test method thereof
12/14/2004	US6832329 Cache thresholding method, apparatus, and program for predictive reporting of array bit line or driver failures
12/14/2004	US6832177 Method of addressing individual memory devices on a memory module
12/14/2004	US6831870 Semiconductor memory
12/14/2004	US6831869 Semiconductor memory device and electronic information device using the same
12/14/2004	US6831868 Byte aligned redundancy for memory array
12/14/2004	US6831859 Non-volatile semiconductor memory for storing initially-setting data
12/14/2004	US6831858 Non-volatile semiconductor memory device and data write control method for the same
12/14/2004	US6831853 Apparatus for cleaning a substrate
12/09/2004	WO2004107350A1 Ferroelectric memory
12/09/2004	WO2004106957A2 Signal integrity self-test architecture
12/09/2004	US20040250182 Computer event log overwriting intermediate events
12/09/2004	US20040250165 Semiconductor memory device permitting boundary scan test
12/09/2004	US20040250160 Method for creating defect management information in an recording medium, and apparatus and medium based on said method
12/09/2004	US20040246804 Device and method for pulse width control in a phase change memory device
12/09/2004	US20040246801 Integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation
12/09/2004	US20040246797 Semiconductor device and test method of testing the same
12/09/2004	US20040246796 Row-column repair technique for semiconductor memory arrays
12/09/2004	US20040246795 SOI substrate and manufacturing method thereof
12/09/2004	US20040246793 Semiconductor memory device
12/09/2004	US20040246792 Integrated memory circuit having a redundancy circuit and a method for replacing a memory area
12/09/2004	US20040246791 Semiconductor memory apparatus and self-repair method
12/09/2004	US20040246789 Silicon plate, method for producing silicon plate, and solar cell
12/09/2004	US20040246781 Permanent master block lock in a memory device
12/09/2004	US20040246774 Memory system
12/09/2004	US20040246773 Test mode decoder in a flash memory
12/09/2004	US20040246772 Method and semiconductor integrated circuit for detecting soft defects in static memory cell
12/09/2004	US20040246337 Self-test executable integrated circuit, a design apparatus thereof, and a scan chain design apparatus
12/09/2004	US20040246045 Voltage and time control circuits and methods of operating the same
12/09/2004	US20040245626 Semiconductor device, system device using it, and manufacturing method of a semiconductor device
12/09/2004	US20040245569 Device architecture and process for improved vertical memory arrays
12/09/2004	US20040245566 Semiconductor integrated circuit and method for detecting soft defects in static memory cell
12/09/2004	DE10335132B3 Memory arrangement for computer system has semiconducting components on memory arrangement that can be tested and adjusted via interface in application-like and unit-specific manner
12/09/2004	DE10321467A1 Test method for characterization of the output circuits of high-speed memory module in which the inputs to the output circuit are temporarily disconnected from their memory cells and instead connected to a test data source
12/09/2004	DE10319516A1 High-speed semiconductor memory modules test method, especially for DDR-DRAM, in which a number of suitable memory control units are selected as test memory control units and provided as part of a test device
12/09/2004	DE10319273A1 Verfahren und Vorrichtung zum Bewerten von einmal programmierbaren Zellen Method and apparatus for evaluating one-time programmable cells
12/09/2004	DE10297319T5 Anwendungsspezifisches ereignisbasiertes Halbleiterspeicher-Testsystem Application-specific event-based semiconductor memory test system
12/09/2004	DE102004023407A1 Integriertes Selbsttestsystem und -verfahren Built-in self-test system and method
12/09/2004	DE102004020875A1 Verfahren und Vorrichtung zum Maskieren bekannter Ausfälle während Speichertestauslesungen Method and apparatus for masking known failures during congestion Stored readings
12/09/2004	DE102004003353A1 Verfahren und System zum Minimieren der Länge einer Defektliste für eine Speichervorrichtung A method and system for minimizing the length of a defect list for a memory device
12/08/2004	EP1483722A1 Memory module assembly using partially defective chips
12/07/2004	US6829739 Apparatus and method for data buffering
12/07/2004	US6829738 Configuration for testing an integrated semiconductor memory and method for testing the memory
12/07/2004	US6829737 Method and system for storing device test information on a semiconductor device using on-device logic for determination of test results
12/07/2004	US6829736 Method of testing a memory
12/07/2004	US6829728 Full-speed BIST controller for testing embedded synchronous memories
12/07/2004	US6829722 System and method of processing memory
12/07/2004	US6829721 Method for recording and storage of system information in multi-board solid-state storage systems
12/07/2004	US6829554 Method for classifying components
12/07/2004	US6829193 Power supply control circuit for use in semiconductor storage device
12/07/2004	US6829183 Active restore weak write test mode
12/07/2004	US6829182 Device for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines

1 ... 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 ... 306