| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
|---|
| 01/11/2005 | US6842041 Low-voltage non-degenerative transmitter circuit |
| 01/11/2005 | US6842031 Method of electrically testing semiconductor devices |
| 01/06/2005 | US20050005230 Semiconductor integrated circuit device and error checking and correcting method thereof |
| 01/06/2005 | US20050005218 Method and apparatus for testing DRAM memory chips in multichip memory modules |
| 01/06/2005 | US20050005210 Semiconductor integrated circuit having a number of data output pins capable of selectively providing output signals and test method thereof |
| 01/06/2005 | US20050005209 Memory bus checking procedure |
| 01/06/2005 | US20050005184 Method for measuring and compensating skews of data transmission lines |
| 01/06/2005 | US20050002262 Pure CMOS latch-type fuse circuit |
| 01/06/2005 | US20050002261 Semiconductor memory device with a bypass circuit for verifying the characteristics of an internal clock signal |
| 01/06/2005 | US20050002247 Shared sense amplifier scheme semiconductor memory device and method of testing the same |
| 01/06/2005 | US20050002245 Method and apparatus for optimizing the functioning of DRAM memory elements |
| 01/06/2005 | US20050002244 Semiconductor storage device, redundancy circuit thereof, and portable electronic device |
| 01/06/2005 | US20050002243 Reduced power redundancy address decoder and comparison circuit |
| 01/06/2005 | US20050002240 Semiconductor memory device and portable electronic apparatus |
| 01/06/2005 | US20050002234 Method and apparatus for dynamically configuring redundant area of non-volatile memory |
| 01/06/2005 | US20050002223 Output driver impedance control for addressable memory devices |
| 01/06/2005 | US20050001283 Semiconductor integrated circuit device and method of testing the same |
| 01/06/2005 | US20050001244 Semiconductor memory device having externally controllable data input and output mode |
| 01/05/2005 | EP1221165A4 Circuit and method for a multiplexed redundancy scheme in a memory device |
| 01/05/2005 | CN1183549C Test device for testing a memory |
| 01/05/2005 | CN1183547C Semiconductor memory device with redundancy memory circuit |
| 01/04/2005 | US6839648 Systems for providing zero latency, non-modulo looping and branching of test pattern data for automatic test equipment |
| 01/04/2005 | US6839397 Circuit configuration for generating control signals for testing high-frequency synchronous digital circuits |
| 01/04/2005 | US6839301 Method and apparatus for improving stability and lock time for synchronous circuits |
| 01/04/2005 | US6839293 Word-line deficiency detection method for semiconductor memory device |
| 01/04/2005 | US6839292 Apparatus and method for parallel programming of antifuses |
| 01/04/2005 | US6839275 Memory system having control circuit configured to receive data, provide encoded received data to match a fault pattern in the array of memory cells |
| 01/04/2005 | US6839266 Memory module with offset data lines and bit line swizzle configuration |
| 01/04/2005 | US6839261 Semiconductor memory device |
| 01/04/2005 | US6839259 Content addressable memory device for compensating faults |
| 01/04/2005 | US6839257 Content addressable memory device capable of reducing memory capacity |
| 01/04/2005 | US6838926 Fuse circuit for semiconductor integrated circuit |
| 01/04/2005 | US6838896 Method and system for probing, testing, burn-in, repairing and programming of integrated circuits in a closed environment using a single apparatus |
| 01/04/2005 | US6838718 Ferroelectric capacitor and ferroelectric memory |
| 12/30/2004 | US20040268275 Analysis of the quality of contacts and vias in multi-metal fabrication processes of semiconductor devices, method and test chip architecture |
| 12/30/2004 | US20040268208 Computation of branch metric values in a data detector |
| 12/30/2004 | US20040268198 Method, system and apparatus for aggregating failures across multiple memories and applying a common defect repair solution to all of the multiple memories |
| 12/30/2004 | US20040268191 Memory unit test |
| 12/30/2004 | US20040268046 Nonvolatile buffered memory interface |
| 12/30/2004 | US20040267481 Apparatus and method for testing memory cards |
| 12/30/2004 | US20040264285 Method and system for saving the state of integrated circuits upon failure |
| 12/30/2004 | US20040264271 Non-volatile semiconductor memory |
| 12/30/2004 | US20040264269 Buffered memory module and method for testing same |
| 12/30/2004 | US20040264265 Apparatus and method of wordline/bitline redundancy control using shift registers in an SRAM |
| 12/30/2004 | US20040264259 Semiconductor memory device |
| 12/30/2004 | US20040264245 Nonvolatile memory and method of restoring of failure memory cell |
| 12/30/2004 | US20040264234 PCRAM cell operation method to control on/off resistance variation |
| 12/30/2004 | US20040264233 Random number generator with ring oscillation circuit |
| 12/30/2004 | US20040264231 Portable electronic device capable of protecting specific block of flash memory chip |
| 12/30/2004 | US20040264227 Semicondutor integrated circuit and electronic system |
| 12/30/2004 | US20040263198 Methods and apparatus for testing electronic circuits |
| 12/30/2004 | US20040262731 Self-testing printed circuit board comprising electrically programmable three-dimensional memory |
| 12/30/2004 | DE10344877B3 Testing and monitoring circuit with interface card for data storage module has motherboard carrying storage module, microcontroller EEPROM, timing generator and interface card voltage source |
| 12/30/2004 | DE10326338A1 Semiconductor component test system has computer using pattern recognition or neural networks to process data from multiple tests on packaged or wafer devices |
| 12/30/2004 | DE10324611A1 Integrierter Halbleiterspeicher und Verfahren zur Reduzierung von Leckströmen in einem Halbleiterspeicher Integrated semiconductor memory and method of reducing leakage current in a semiconductor memory, |
| 12/30/2004 | DE102004026521A1 Dynamic RAM test device selects address of address pointer and pattern generator while generating back pattern after count of defective number of bits, for output to failed memory |
| 12/30/2004 | DE102004025975A1 Programming method for phase-change random access memory device, involves removing set pulse when memory device is determined to be in desired set state such that duration of set pulse is controlled based on state of memory device |
| 12/29/2004 | WO2004114319A2 Apparatus and method for testing memory cards |
| 12/29/2004 | WO2004114318A1 Semiconductor test device and control method thereof |
| 12/29/2004 | WO2004114317A1 Test device and program |
| 12/29/2004 | WO2004114135A1 Failure detection method and device for a cache memory, and corresponding cache memory |
| 12/29/2004 | EP1490905A1 Interconnection structure and methods |
| 12/29/2004 | CN1182539C Semiconductor storage and its ageing sieving method |
| 12/29/2004 | CN1182537C Semiconductor integrated circuit device capable of inhibiting noise and supplying power potential |
| 12/29/2004 | CN1182536C Parallel redundant method and apparatus for semi-conductor storage |
| 12/29/2004 | CN1182534C Chip of semiconductor memory |
| 12/28/2004 | US6836863 Semiconductor memory testing method and apparatus |
| 12/28/2004 | US6836861 Efficient memory allocation scheme for data collection |
| 12/28/2004 | US6836445 Memory device in semiconductor for enhancing ability of test |
| 12/28/2004 | US6836441 Apparatus of repairing memory cell and method therefor |
| 12/28/2004 | US6836440 Method of checking electrical connections between a memory module and a semiconductor memory chip |
| 12/28/2004 | US6836439 Ferroelectric memory device comprising redundancy circuit |
| 12/28/2004 | US6836438 Method and apparatus for dynamically hiding a defect in an embedded memory |
| 12/28/2004 | US6836425 Coding cell of nonvolatile ferroelectric memory device and operating method thereof, and column repair circuit of nonvolatile ferroelectric memory device having the coding cell and method for repairing column |
| 12/28/2004 | US6836146 Built-in self repair for an integrated circuit |
| 12/28/2004 | US6836138 Module having test architecture for facilitating the testing of ball grid array packages, and test method using the same |
| 12/28/2004 | US6836106 Apparatus and method for testing semiconductors |
| 12/28/2004 | US6836104 Internal power supply voltage control apparatus having two internal power supply reference voltage generating circuits |
| 12/23/2004 | WO2004038561A3 Reliable and secure updating and recovery of firmware from a mass storage device |
| 12/23/2004 | US20040261049 Circuit and method for error test, recordation, and repair |
| 12/23/2004 | US20040260988 Semiconductor memory, system for testing a memory cell, and method for testing a memory cell |
| 12/23/2004 | US20040260987 Memory module, test system and method for testing one or a plurality of memory modules |
| 12/23/2004 | US20040260986 Programmable weak write test mode (PWWTM) bias generation having logic high output default mode |
| 12/23/2004 | US20040260983 Latched sense amplifiers as high speed memory in a memory system |
| 12/23/2004 | US20040260975 Semiconductor integrated circuit |
| 12/23/2004 | US20040260934 Memory chip having an integrated address scrambler unit and method for scrambling an address in an integrated memory |
| 12/23/2004 | US20040257901 Memory repair circuit and method |
| 12/23/2004 | US20040257893 Method and test circuit for testing a dynamic memory circuit |
| 12/23/2004 | US20040257892 Method and apparatus for improving the reliability of the reading of integrated circuit fuses |
| 12/23/2004 | US20040257891 Self-repairing built-in self test for linked list memories |
| 12/23/2004 | US20040257888 Data storage system |
| 12/23/2004 | US20040257886 Redundancy circuit for memory array and method for disabling non-redundant wordlines and for enabling redundant wordlines |
| 12/23/2004 | US20040257885 Semiconductor memory device |
| 12/23/2004 | US20040257882 Bias generation having adjustable range and resolution through metal programming |
| 12/23/2004 | US20040257850 Method for testing a memory device |
| 12/23/2004 | US20040257106 Semiconductor device for reducing the number of probing pad used during wafer test and method for testing the same |
| 12/23/2004 | US20040257104 Evaluation device for evaluating semiconductor device |
| 12/23/2004 | US20040257103 Module having test architecture for facilitating the testing of ball grid array packages, and test method using the same |
| 12/23/2004 | US20040256638 Configurable width buffered module having a bypass circuit |
| 12/23/2004 | DE10324080A1 Testing and control process for electronic chips such as logic or memory chips individually compares test data with identifying unit and operates command block or deactivates failures |