| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 02/24/2005 | US20050043912 Memory testing apparatus and method |
| 02/24/2005 | US20050043908 Circuits and methods for characterizing random variations in device characteristics in semiconductor integrated circuits |
| 02/24/2005 | US20050041519 Integrated clock supply chip for a memory module, memory module comprising the integrated clock supply chip, and method for operating the memory module under test conditions |
| 02/24/2005 | US20050041504 Method of operating a memory system including an integrated circuit buffer device |
| 02/24/2005 | US20050041497 Integrated memory having a test circuit for functional testing of the memory |
| 02/24/2005 | US20050041493 Semiconductor storage device |
| 02/24/2005 | US20050041492 Redundancy circuit |
| 02/24/2005 | US20050041491 Repair apparatus and method for semiconductor memory device to be selectively programmed for wafer-level test or post package test |
| 02/24/2005 | US20050041485 Adjustable timing circuit of an integrated circut |
| 02/24/2005 | US20050041460 Method and circuit for scan testing latch based random access memory |
| 02/24/2005 | US20050040840 Method for monitoring quality of an insulation layer |
| 02/24/2005 | US20050040830 Integrated circuit for testing circuit components of a semiconductor chip |
| 02/24/2005 | US20050040398 Test structure for improved vertical memory arrays |
| 02/24/2005 | DE10311373B4 Integrierter Speicher mit redundanten Einheiten von Speicherzellen und Verfahren zum Test eines integrierten Speichers Integrated memory having redundant units of memory cells and methods for testing an integrated memory |
| 02/24/2005 | DE102004034184A1 Ein System von multiplexierten Datenleitungen in einem dynamischen Direktzugriffsspeicher A system of multiplexed data lines in a dynamic random access memory |
| 02/24/2005 | DE10064478B4 Verfahren zur Prüfung einer integrierten Schaltung und Schaltungsanordnung A method for testing an integrated circuit and the circuit arrangement |
| 02/23/2005 | CN1585987A Memory unit test |
| 02/23/2005 | CN1190834C Method of release charge accumulation of non-volatile storage structure |
| 02/22/2005 | US6859904 Apparatus and method to facilitate self-correcting memory |
| 02/22/2005 | US6859901 Method for testing memories with seamless data input/output by interleaving seamless bank commands |
| 02/22/2005 | US6859401 Fail number detecting circuit of flash memory |
| 02/22/2005 | US6859070 Semiconductor integrated circuit device having flip-flops that can be reset easily |
| 02/22/2005 | US6859067 Semiconductor apparatus |
| 02/22/2005 | US6859059 Systems and methods for testing receiver terminations in integrated circuits |
| 02/22/2005 | US6858916 Semiconductor memory device with series-connected antifuse-components |
| 02/22/2005 | US6858450 Method of alternating grounded/floating poly lines to monitor shorts |
| 02/22/2005 | US6858448 Method for evaluating and manufacturing a semiconductor device |
| 02/22/2005 | US6858447 Method for testing semiconductor chips |
| 02/17/2005 | WO2005015569A2 Hub module for connecting one or more memory devices, comprising an address decoder unit for addressing redundant memory areas |
| 02/17/2005 | WO2005015568A1 Memory device and method of storing fail addresses of a memory cell |
| 02/17/2005 | US20050039174 Apparatus and method for co-simulating processors and DUT modules |
| 02/17/2005 | US20050039100 Method and system for automatic error recovery in an electronic mail system |
| 02/17/2005 | US20050039090 Non-volatile memory with network fail-over |
| 02/17/2005 | US20050039089 System and method for analysis of cache array test data |
| 02/17/2005 | US20050039073 Integrated memory having a circuit for testing the operation of the integrated memory, and method for operating the integrated memory |
| 02/17/2005 | US20050038956 Method and an apparatus of flash cards access |
| 02/17/2005 | US20050038633 System and method for analysis of cache array test data |
| 02/17/2005 | US20050036453 Controlling method and device for data transmission |
| 02/17/2005 | US20050036397 Detecting device and method for determining type and insertion of flash memory card |
| 02/17/2005 | US20050036374 Probe card substrate |
| 02/17/2005 | US20050036371 Semiconductor memory including error correction function |
| 02/17/2005 | US20050036362 Semiconductor memory device having memory cells including ferromagnetic films and control method thereof |
| 02/17/2005 | US20050036355 Semiconductor memory device capable of testing data line redundancy replacement circuit |
| 02/17/2005 | US20050036259 Reduced power consumption in integrated circuits with fuse controlled redundant circuits |
| 02/17/2005 | US20050035785 Logic circuit and semiconductor integrated circuit |
| 02/17/2005 | DE10350356B3 Integrated circuit e.g. memory circuit, with test circuit for read-out of fault data during test mode supplying fault data to alternate data outputs in response to different read commands |
| 02/17/2005 | DE10331543A1 Verfahren zum Testen einer zu testenden Schaltungseinheit und Schaltungsanordnung zur Durchführung des Verfahrens A method of testing a circuit under test unit and circuit arrangement for carrying out the method |
| 02/17/2005 | DE10331068A1 Verfahren zum Auslesen von Fehlerinformationen aus einem integrierten Baustein und integrierter Speicherbaustein A method for extraction of fault information from an integrated module and an integrated memory chip |
| 02/17/2005 | DE102004035151A1 Spannungserhöhungsschaltung und -verfahren Voltage step-up circuit and method |
| 02/16/2005 | EP1506552A1 Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data |
| 02/16/2005 | EP0965995B1 Circuit and method for automatic detection and correction of short circuits between wordlines and bitlines |
| 02/16/2005 | CN1581360A 逻辑电路和半导体集成电路 A logic circuit and a semiconductor integrated circuit |
| 02/16/2005 | CN1581339A Data with multiple sets of error correction codes |
| 02/16/2005 | CN1581102A Circuit and method for implementing correction operation to only read memory in inlaid program |
| 02/16/2005 | CN1581092A Memory arrangement in a computer system |
| 02/16/2005 | CN1189891C Examination method integrated circuit |
| 02/16/2005 | CN1189890C Semiconductor memory device with multiple low-pissipation module type |
| 02/15/2005 | US6856569 Method and system for merging multiple fuse decompression serial bitstreams to support auxiliary fuseblow capability |
| 02/15/2005 | US6856567 Semiconductor device with self refresh test mode |
| 02/15/2005 | US6856562 Test structure for measuring a junction resistance in a DRAM memory cell array |
| 02/15/2005 | US6856561 Semiconductor memory device |
| 02/15/2005 | US6856560 Redundancy in series grouped memory architecture |
| 02/10/2005 | WO2005013285A1 Modular test controller with bist circuit for testing embedded dram circuits |
| 02/10/2005 | WO2004109706A3 Nanoscale wire-based sublithographic programmable logic arrays |
| 02/10/2005 | US20050034085 System and method for enabling a vendor mode on an integrated circuit |
| 02/10/2005 | US20050034040 System and method for self-adaptive redundancy choice logic |
| 02/10/2005 | US20050034037 Methods and apparatus for testing integrated circuits |
| 02/10/2005 | US20050034025 Adapter card for connection to a data bus in a data processing unit and method for operating a DDR memory module |
| 02/10/2005 | US20050034021 Semiconductor device and method for testing the same |
| 02/10/2005 | US20050033949 Test method, test receptacle and test arrangement for high-speed semiconductor memory devices |
| 02/10/2005 | US20050033903 Integrated circuit device |
| 02/10/2005 | US20050033898 Method of efficiently loading scan and non-scan memory elements |
| 02/10/2005 | US20050033541 Memory cell signal window testing apparatus |
| 02/10/2005 | US20050030831 Hardware and software programmable fuses for memory repair |
| 02/10/2005 | US20050030822 Apparatus and method for reading out defect information items from an integrated chip |
| 02/10/2005 | US20050030815 Semiconductor memory module |
| 02/10/2005 | US20050030802 Memory module including an integrated circuit device |
| 02/10/2005 | US20050030799 Logical data block, magnetic random access memory, memory module, computer system and method |
| 02/10/2005 | US20050030796 Circuit and/or method for implementing a patch mechanism for embedded program ROM |
| 02/10/2005 | US20050030781 Method and arrangement for testing output circuits of high speed semiconductor memory devices |
| 02/10/2005 | US20050030074 Semiconductor device having PLL-circuit |
| 02/10/2005 | US20050030055 Integrated circuit with test pad structure and method of testing |
| 02/10/2005 | DE60008789T2 Bitfehlerkarten-kompression mit signaturanalyse Bitfehlerkarten-compression with signature analysis |
| 02/10/2005 | DE10343388A1 Integrated circuit with fuse memory permanently storing setting value for integrated circuit after integrated circuit testing |
| 02/10/2005 | DE10330593A1 Integrated clock-pulse supply module for memory module, has phase control loop connected to clock signal input and generating second clock signal |
| 02/10/2005 | DE10303963B4 Integrierte Schaltungsanordnung An integrated circuit device |
| 02/10/2005 | DE102004033444A1 Integrierter Speicherschaltungsbaustein Integrated circuit memory block |
| 02/10/2005 | DE102004027883A1 Integrierte Speicherschaltungsbausteine und Betriebsverfahren, die ausgeführt sind, um Datenbits mit einer niedrigeren Rate in einer Testbetriebsart auszugeben An integrated circuit memory devices and operating procedures that are designed to output data bits at a lower rate in a test mode |
| 02/10/2005 | DE102004014450A1 Measuring and compensating method of skews in dual in-line memory module, involves calculating relative skew of each data transmission line with respect to slowest data transmission line |
| 02/09/2005 | EP1505608A1 Memory system with error detection device |
| 02/09/2005 | CN2678012Y Embedded computer system with real-time error detection and correction function |
| 02/09/2005 | CN1577846A Semicondutor integrated circuit and electronic system |
| 02/09/2005 | CN1577800A Read/program potential generating circuit |
| 02/09/2005 | CN1577784A Writing buffer-supporting FLASH internal unit testing metod |
| 02/09/2005 | CN1577634A 半导体装置 Semiconductor device |
| 02/09/2005 | CN1577633A Method for reading out defect information item of self integrated chip and integrated memory chip |
| 02/09/2005 | CN1577632A 半导体集成电路装置 The semiconductor integrated circuit device |
| 02/09/2005 | CN1577631A Method for testing a circuit which is under test, and circuit configuration for carrying out the method |
| 02/09/2005 | CN1577630A Semiconductor circuit and method for testing, monitoring and application-near setting of a semiconductor circuit |
| 02/09/2005 | CN1577629A FLASH internal unit testing method |