Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
04/2005
04/19/2005US6882202 Multiple trip point fuse latch device and method
04/14/2005WO2005034176A2 Apparatus and method for selectively configuring a memory device using a bi-stable relay
04/14/2005WO2005034130A1 Accelerated life test of mram celles
04/14/2005WO2005034123A1 Method and apparatus for error code correction
04/14/2005WO2005033949A1 Semiconductor memory device
04/14/2005US20050081133 Method and test drive for detecting addressing errors in control devices
04/14/2005US20050081132 Method and apparatus for error code correction
04/14/2005US20050081093 Ternary content addressable memory directed associative redundancy for semiconductor memories
04/14/2005US20050080581 Built-in self test for memory interconnect testing
04/14/2005US20050078548 Method and memory system in which operating mode is set using address signal
04/14/2005US20050078545 Method and circuit for controlling generation of column selection line signal
04/14/2005US20050078536 Resistive cross point memory
04/14/2005US20050078523 Non-volatile semiconductor memory device
04/14/2005US20050078515 Non-volatile memory with test rows for disturb detection
04/14/2005US20050078500 Backside of chip implementation of redundancy fuses and contact pads
04/14/2005US20050077975 Circuits and methods of temperature compensation for refresh oscillator
04/14/2005US20050077923 Voltage trimming circuit
04/14/2005US20050077600 Semiconductor device
04/13/2005EP1521974A2 Electronic circuit with test unit for testing interconnects
04/13/2005CN1606091A Integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate
04/12/2005US6880117 Memory device test system and method
04/12/2005US6880060 Method for storing metadata in a physical sector
04/12/2005US6879530 Apparatus for dynamically repairing a semiconductor memory
04/12/2005US6879529 Semiconductor memory having a defective memory cell relieving circuit
04/12/2005US6879526 Methods and apparatus for improved memory access
04/12/2005US6879207 Defect tolerant redundancy
04/12/2005US6879038 Method and apparatus for hermetic sealing of assembled die
04/12/2005US6877897 Method for determining the temperature of a memory cell from transistor threshold voltage
04/07/2005WO2005031754A1 Nonvolatile semiconductor memory device having protection function for each memory block
04/07/2005WO2004102216A3 Test systems and methods
04/07/2005US20050076281 Network terminal that notifies administrator of error
04/07/2005US20050076277 Test apparatus with static storage device and test method
04/07/2005US20050076274 Semiconductor integrated circuit
04/07/2005US20050076273 Testing CMOS ternary CAM with redundancy
04/07/2005US20050076268 RAM diagnostic read circuit providing external integrated circuit RAM failure diagnosis and method
04/07/2005US20050073893 Memory bit line leakage repair
04/07/2005US20050073891 Semiconductor memory device and method for testing same
04/07/2005US20050073890 System and method of calibrating a read circuit in a magnetic memory
04/07/2005US20050073885 Semiconductor memory device
04/07/2005US20050073875 Redundancy repaired yield calculation method
04/07/2005US20050073353 Circuit of redundancy IO fuse in semiconductor device
04/07/2005US20050073332 Semiconductor testing apparatus
04/07/2005DE10340917A1 Test method for output signals of integrated circuit e.g. for dynamic memory modules, integrated circuit has terminals for applying first- and second-data signals
04/07/2005DE102004037920A1 Speicherzellensignalfenstertestvorrichtung Memory cell signal window test device
04/07/2005DE10131675B4 Schaltungsanordnung und Verfahren zur Ermittlung einer Zeitkonstante eines Speicherkondensators einer Speicherzelle eines Halbleiterspeichers Circuit arrangement and method for determining a time constant of a storage capacitor of a memory cell of a semiconductor memory
04/06/2005EP1520183A2 Single pin multilevel integrated circuit test interface
04/06/2005CN1604322A 半导体器件 Semiconductor devices
04/06/2005CN1604297A Semiconductor device and method for producing the same
04/06/2005CN1604235A Testing device possessing static storage device and testing method
04/06/2005CN1604234A Semiconductor device and method for testing semiconductor device
04/06/2005CN1196199C Nonvolatile semiconductor memory device and its imperfect repairing method
04/05/2005US6877128 Weighted error/erasure correction in a multi-track storage medium
04/05/2005US6877118 Memory testing method and memory testing apparatus
04/05/2005US6877103 Bus interface timing adjustment device, method and application chip
04/05/2005US6877100 Adjustable timing circuit of an integrated circuit by selecting and moving clock edges based on a signal propagation time stored in a programmable non-volatile fuse circuit
04/05/2005US6877078 Information processing system with memory element performance-dependent memory control
04/05/2005US6876594 Integrated circuit with programmable fuse array
04/05/2005US6876592 Semiconductor memory device
04/05/2005US6876591 Integrated circuit with self-test device for an embedded non-volatile memory and related test method
04/05/2005US6876590 2T2C signal margin test mode using a defined charge exchange between BL and/BL
04/05/2005US6876588 Semiconductor storage device formed to optimize test technique and redundancy technology
04/05/2005US6876586 Shift register chain for trimming generators for an integrated semiconductor apparatus
04/05/2005US6876580 Semiconductor memory device having a burst continuous read function
04/05/2005US6876576 Thin film magnetic memory device having redundant configuration
04/05/2005US6876564 Integrated circuit device and method for applying different types of signals to internal circuit via one pin
04/05/2005US6876221 Fault tolerant semiconductor system
04/05/2005US6876219 Test configuration with automatic test machine and integrated circuit and method for determining the time behavior of an integrated circuit
04/05/2005US6876217 Method for testing semiconductor circuit devices
04/05/2005US6876057 Semiconductor devices including fuses and dummy fuses
03/2005
03/31/2005WO2005029505A1 Memory device
03/31/2005WO2005029504A2 Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance
03/31/2005WO2004106957A3 Signal integrity self-test architecture
03/31/2005WO2004102631A3 Reference current generator, and method of programming, adjusting and/or operating same
03/31/2005WO2004044752A3 Memory controllers with interleaved mirrored memory modes
03/31/2005WO2004010321A3 Processor array
03/31/2005US20050071732 Data recording method for optical disk drive
03/31/2005US20050071731 Method, system, and apparatus for supporting power loss recovery in ECC enabled memory devices
03/31/2005US20050071722 Data processing apparatus and method for handling corrupted data values
03/31/2005US20050071718 Memory integrity self checking in VT/TU cross-connect
03/31/2005US20050071717 Method and apparatus for low overhead circuit scan
03/31/2005US20050071712 Testing memory units in a digital circuit
03/31/2005US20050071580 Distributed memory initialization and test methods and apparatus
03/31/2005US20050071540 Memory device with a flexible reduced density option
03/31/2005US20050068841 Integrated memory and method for functional testing of the integrated memory
03/31/2005US20050068838 Semiconductor memory device allowing accurate burn-in test
03/31/2005US20050068818 Semiconductor device and method for testing semiconductor device
03/31/2005US20050068817 Circuit arrangement for setting a voltage supply for a test mode of an integrated memory
03/31/2005US20050068816 Semiconductor memory device and method of testing the device
03/31/2005US20050068815 Accelerated life test of mram cells
03/31/2005US20050068082 Method and apparatus for accommodating delay variations among multiple signals
03/31/2005US20050068055 Test arrangement for testing semiconductor circuit chips
03/31/2005US20050067899 Semiconductor device and method for producing the same
03/31/2005DE10338678A1 Vorrichtung und Verfahren zum Testen von zu testenden Schaltungseinheiten Apparatus and method for testing the circuit under test units
03/31/2005DE10338022A1 Memory addressing method for memory areas in a memory circuit uses sequential addresses to address controllable or redundant memory areas by relying on an address
03/31/2005DE10337854A1 Integrierter Speicher mit einer Testschaltung zum Funktionstest des Speichers Built-in memory with a test circuit for functional test of the memory
03/31/2005DE102004039831A1 Multi-chip module with semiconductor store, includes comparator coupled to non-volatile store for comparing address at write/read accesses with stored address
03/30/2005EP1518181A1 Method and apparatus for optimizing timing for a multi-drop bus
03/30/2005CN1601717A Probe card substrate
03/30/2005CN1601652A Semiconductor memory device and method of testing the device
03/30/2005CN1601480A Device for testing storage modular
1 ... 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 ... 306