Patents
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
05/2005
05/05/2005US20050094951 Method and apparatus for hermetic sealing of assembled die
05/05/2005US20050094514 Method and apparatus for generating the wobble clock signal
05/05/2005US20050094478 Non-volatile semiconductor memory
05/05/2005US20050094476 Semiconductor memory device using ferroelectric capacitor, and semiconductor device with the same
05/05/2005US20050094451 Method of detecting errors in a priority encoder and a content addressable memory adopting the same
05/05/2005US20050094450 Semiconductor device and testing apparatus for semiconductor device
05/05/2005US20050094448 Integrated circuit device with on-chip setup/hold measuring circuit
05/05/2005US20050094440 Error recovery for nonvolatile memory
05/05/2005US20050094439 Non-voltile memory test structure and method
05/05/2005US20050094432 Multi-mode synchronous memory device and methods of operating and testing same
05/05/2005US20050093564 Signal test procedure for testing semi-conductor components and a test apparatus for testing semi-conductor components
05/04/2005DE10340437B3 Signal comparison circuit device for testing read-only memory cells with comparator circuit and output circuit using 4 controlled current paths
05/04/2005DE10042620B4 Anordnung zum Testen eines Speichermoduls Arrangement for testing a memory module
05/04/2005CN1613119A Dual mode high voltage power supply for providing increased speed in programming during testing of low voltage non-volatile memories
05/04/2005CN1612265A Semiconductor memory device and method for manufacturing same
05/04/2005CN1612119A Solid state storage unit safety storage system and method
05/04/2005CN1200281C Specific purpose semiconductor memory testing system based on event
05/03/2005US6889352 Digital signal forming method, disc recording media using the same, and reproducing method thereof
05/03/2005US6889307 Integrated circuit incorporating dual organization memory array
05/03/2005US6889305 Device identification using a memory profile
05/03/2005US6888775 Semiconductor memory device for improvement of defective data line relief rate
05/03/2005US6888774 Semiconductor memory device and its testing method
05/03/2005US6888766 Semiconductor memory device provided with test memory cell unit
05/03/2005US6888764 Semiconductor device including semiconductor memory
05/03/2005US6888762 Apparatus for reducing bleed currents within a DRAM array having row-to-column shorts
05/03/2005US6888751 Nonvolatile semiconductor memory device
05/03/2005US6888731 Method and apparatus for replacing defective rows in a semiconductor memory array
05/03/2005US6888366 Apparatus and method for testing a plurality of semiconductor chips
05/03/2005US6888216 Circuit having make-link type fuse and semiconductor device having the same
04/2005
04/28/2005WO2004072660A3 Compressing test responses using a compactor
04/28/2005US20050091569 System and method for securely storing data in a memory
04/28/2005US20050091563 On chip diagnosis block with mixed redundancy
04/28/2005US20050091561 Scan test method, device, and system
04/28/2005US20050091560 System for optimizing anti-fuse repair time using fuse id
04/28/2005US20050088904 Systems for Built-In-Self-Test for content addressable memories and methods of operating the same
04/28/2005US20050088891 [device and method for breaking leakage current path of memory device and structure of memory device]
04/28/2005US20050088888 Method for testing embedded DRAM arrays
04/28/2005US20050088887 High efficiency redundancy architecture in SRAM compiler
04/28/2005US20050088877 Nonvolatile semiconductor memory device containing reference capacitor circuit
04/28/2005US20050088874 Semiconductor memory having a spare memory cell
04/28/2005US20050088871 Semiconductor device and method of inspecting the same
04/28/2005US20050088870 Semiconductor device and method for testing the same
04/28/2005US20050088150 I/O interface circuit of integrated circuit
04/27/2005EP1526549A1 System and method of calibrating a read circuit in a magnetic memory
04/27/2005EP1526548A1 Improved bit line discharge method and circuit for a semiconductor memory
04/27/2005EP1526458A2 Column redundancy circuit with reduced signal path delay
04/27/2005EP1483722A4 Memory module assembly using partially defective chips
04/27/2005CN1610938A Write-once type optical disc, and method and apparatus for managing defective areas on write-once type optical disc
04/27/2005CN1610834A Method and apparatus for optimized parallel testing and access of electronic circuits
04/27/2005CN1610086A Test sample for bridging and continuous testing
04/27/2005CN1610007A Antifuse programming circuit in which one stage of transistor is interposed in a series with antifuse between power supplies during programming
04/27/2005CN1199275C Semiconductor memory
04/27/2005CN1199267C Electric fuse with close space length and its production method in semiconductor
04/27/2005CN1199190C Memory with word line voltage control and testing method thereof
04/27/2005CN1199188C Semi-conductor storage with block unit to erase
04/27/2005CN1199185C Integrated storage with storage unit having magnetic resistance storage effect
04/27/2005CN1199182C Semiconductor storage adopting reductant mode
04/26/2005US6886120 Memory control circuit
04/26/2005US6886119 Method and apparatus for improved integrated circuit memory testing
04/26/2005US6886117 Field repairable embedded memory in system-on-a-chip
04/26/2005US6886071 Status register to improve initialization of a synchronous memory
04/26/2005US6885959 Circuit and method for calibrating DRAM pullup Ron to pulldown Ron
04/26/2005US6885956 Semiconductor test apparatus
04/26/2005US6885606 Synchronous semiconductor memory device with a plurality of memory banks and method of controlling the same
04/26/2005US6885599 Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device
04/26/2005US6885598 Shared sense amplifier scheme semiconductor memory device and method of testing the same
04/26/2005US6885597 Sensing test circuit
04/26/2005US6885596 Apparatus and method of wordline/bitline redundancy control using shift registers in an SRAM
04/26/2005US6885238 Clamp circuit with fuse options
04/26/2005US6885235 Semiconductor integrated circuit device with internal power supply potential generation circuit
04/26/2005US6885208 Semiconductor device and test device for same
04/26/2005US6885203 Wafer level burn-in using light as the stimulating signal
04/21/2005US20050086575 Generalized parity stripe data storage array
04/21/2005US20050086574 Error correction for multi-level cell memory with overwrite capability
04/21/2005US20050086572 Semiconductor device having ECC circuit
04/21/2005US20050086564 Multi-chip module and method for testing
04/21/2005US20050086559 Storage system using fast storage devices for storing redundant data
04/21/2005US20050086037 Memory device load simulator
04/21/2005US20050083748 Magnetic memory having a calibration system
04/21/2005US20050083739 Apparatus and method for dynamically repairing a semiconductor memory
04/21/2005US20050083726 Soft errors handling EEPROM devices
04/21/2005US20050083717 Antifuse programming circuit in which one stage of transistor is interposed in a series with antifuse between power supplies during programming
04/21/2005US20050083078 Test key for bridge and continuity testing
04/21/2005US20050082641 Flexible and elastic dielectric integrated circuit
04/21/2005US20050082626 Membrane 3D IC fabrication
04/21/2005DE4422786B4 Speichersystem Storage system
04/21/2005DE10338677B3 Verfahren zum Testen einer zu testenden Schaltungseinheit und Testvorrichtung A method of testing a circuit under test unit and test device
04/21/2005DE10323865B4 Integrierte Schaltung, insbesondere integrierter Speicher, sowie Verfahren zum Betrieb einer integrierten Schaltung Integrated circuit, particularly an integrated memory, and method for operating an integrated circuit
04/20/2005CN1607666A Circuit arrangement for setting a voltage supply for a test mode of an integrated memory
04/20/2005CN1607609A EEPROM array with flash-like core
04/20/2005CN1607396A Semi-conductor component test process and a system for testing semi-conductor components
04/19/2005US6883129 Electronic circuit and method for testing
04/19/2005US6883128 PC and ATE integrated chip test equipment
04/19/2005US6882592 Semiconductor memory device
04/19/2005US6882591 Synchronous controlled, self-timed local SRAM block
04/19/2005US6882587 Method of preparing to test a capacitor
04/19/2005US6882586 Semiconductor memory device equipped with control circuit for controlling memory cell array in non-normal operation mode
04/19/2005US6882585 ROM memory device having repair function for defective cell and method for repairing the defective cell
04/19/2005US6882583 Method and apparatus for implementing DRAM redundancy fuse latches using SRAM
04/19/2005US6882557 Semiconductor memory device