Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
03/2005
03/30/2005CN1195325C 半导体集成电路及其测试方法 Semiconductor integrated circuit and test methods
03/29/2005US6874116 Masking error detection/correction latency in multilevel cache transfers
03/29/2005US6874111 System initialization of microcode-based memory built-in self-test
03/29/2005US6874092 Method and apparatus for erasing data after tampering
03/29/2005US6874073 Method for managing data stored primarily in a read-only memory
03/29/2005US6873557 Integrated circuit device with a built-in detecting circuit for detecting maximum memory access time of an embedded memory
03/29/2005US6873556 Semiconductor memory device with test mode and testing method thereof
03/29/2005US6873549 Writable tracking cells
03/29/2005US6873543 Memory device
03/29/2005US6873173 Test circuit arrangement and method for testing a multiplicity of transistors
03/29/2005US6872583 Test structure for high precision analysis of a semiconductor
03/24/2005WO2005027140A1 Signal margin test mode for feram with ferroelectric reference capacitor.
03/24/2005WO2005027139A1 Management of defective blocks in flash memories
03/24/2005WO2005027134A2 Multiple bit chalcogenide storage device
03/24/2005WO2005027098A2 Method of increasing capacity of an optical disc
03/24/2005WO2005026966A1 Register file and its storage element
03/24/2005WO2004061602A3 Method and apparatus for testing embedded cores
03/24/2005US20050066254 Error detection in redundant array of storage units
03/24/2005US20050066253 System and method for detecting multiple data bit errors in memory
03/24/2005US20050066247 Full-speed BIST controller for testing embedded synchronous memories
03/24/2005US20050066243 Mechanism to enhance observability of integrated circuit failures during burn-in tests
03/24/2005US20050066226 Redundant memory self-test
03/24/2005US20050066224 Method and device for correcting errors in a digital memory
03/24/2005US20050065761 [integrated circuit and method for simulating and trimming thereof]
03/24/2005US20050063230 Semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory
03/24/2005US20050063229 Method of driving and testing a semiconductor memory device
03/24/2005US20050063213 Signal margin test mode for FeRAM with ferroelectric reference capacitor
03/24/2005DE10338079A1 Semiconductor chip test system has shared driver amplifier with decoupling circuits in parallel subchannels applied to chip inputs
03/24/2005CA2538142A1 Multiple bit chalcogenide storage device
03/24/2005CA2536994A1 Management of defective blocks in flash memories
03/23/2005EP1517336A2 Method for facilitating error detection for content addressable memory
03/23/2005EP1517335A2 An improved semiconductor memory device providing redundancy
03/23/2005EP1517334A1 On-chip diagnosis method and on-chip diagnosis block for memory repair with mixed redundancy (IO redundancy and word-register redundancy)
03/23/2005EP1517327A2 High-speed error correcting apparatus with efficient data transfer
03/23/2005EP1516192A1 Test method for yielding a known good die
03/23/2005EP0858630B1 Method, system and apparatus for efficiently generating binary numbers for testing storage devices
03/23/2005CN1598967A System and method for detecting multiple data bit errors in memory
03/22/2005US6871307 Efficient test structure for non-volatile memory and other semiconductor integrated circuits
03/22/2005US6871306 Method and device for reading and for checking the time position of data response signals read out from a memory module to be tested
03/22/2005US6871297 Power-on state machine implementation with a counter to control the scan for products with hard-BISR memories
03/22/2005US6871168 Failure analysis system of semiconductor memory device
03/22/2005US6870787 Configuration and method for checking an address generator
03/22/2005US6870786 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used
03/22/2005US6870783 Mode entrance control circuit and mode entering method in semiconductor memory device
03/22/2005US6870782 Row redundancy memory repair scheme with shift to eliminate timing penalty
03/22/2005US6870781 Semiconductor device verification system and method
03/22/2005US6870780 Semiconductor memory device having improved redundancy scheme
03/22/2005US6870770 Method and architecture to calibrate read operations in synchronous flash memory
03/22/2005US6870754 Ferroelectric memory
03/22/2005US6870750 DRAM array and computer system
03/22/2005US6870749 Content addressable memory (CAM) devices with dual-function check bit cells that support column redundancy and check bit cells with reduced susceptibility to soft errors
03/22/2005US6870392 Method for generating test signals for an integrated circuit and test logic unit
03/22/2005US6870383 Semiconductor device with high speed switching of test modes
03/17/2005WO2005024844A1 Semiconductor memory
03/17/2005WO2005024843A1 Integrated circuit and a method of cache remapping
03/17/2005US20050060631 Facilitating error detection for content addressable memory
03/17/2005US20050060621 Method and system for direct access memory testing of an integrated circuit
03/17/2005US20050060620 Method of increasing capacity of an optical disc
03/17/2005US20050060602 Memory system with error detection device
03/17/2005US20050060601 Apparatus and method for selectively configuring a memory device using a bi-stable relay
03/17/2005US20050060504 Efficient memory allocation scheme for data collection
03/17/2005US20050059175 Dynamic integrated circuit clusters, modules including same and methods of fabricating
03/17/2005US20050058077 Fast-path implementation for an uplink double tagging engine
03/17/2005US20050058008 Soft errors handling in eeprom devices
03/17/2005US20050058007 Method for testing a circuit unit to be tested, and a test apparatus
03/17/2005US20050058006 Semiconductor device, method for testing the same and IC card
03/17/2005US20050058005 Method for operating a memory device
03/17/2005US20050057997 Non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in short period of time
03/17/2005US20050057996 Semiconductor memory device for improving access time in burst mode
03/17/2005US20050057994 Non-volatile semiconductor memory device with expected value comparison capability
03/17/2005US20050057988 Method and device for testing semiconductor memory devices
03/17/2005US20050057985 Method and apparatus for dynamically hiding a defect in an embedded memory
03/17/2005US20050057974 System and method for determining the value of a memory element
03/17/2005US20050057970 Nonvolatile memory device includng circuit formed of thin film transistors
03/17/2005US20050057968 Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance
03/17/2005US20050057963 Semiconductor memory device having memory block configuration
03/17/2005US20050057961 Semiconductor memory device providing redundancy
03/17/2005US20050057959 Method of manufacturing a DRAM array
03/17/2005US20050057272 Method and apparatus for testing semiconductor devices using an actual board-type product
03/17/2005US20050056945 Dynamic integrated circuit clusters, modules including same and methods of fabricating
03/17/2005DE10337284A1 Integrierter Speicher mit einer Schaltung zum Funktionstest des integrierten Speichers sowie Verfahren zum Betrieb des integrierten Speichers Integrated memory having a circuit for a function test of the integrated memory and method of operating the built-in memory
03/17/2005DE10335708A1 Hub-Baustein zum Anschließen von einem oder mehreren Speicherbausteinen Hub module for connecting one or more storage devices
03/17/2005DE102004041020A1 Reparaturvorrichtung und -verfahren und zugehöriger Halbleiterspeicherbaustein Repair apparatus and method and related semiconductor memory device
03/17/2005DE102004040962A1 Compensating circuit for semiconductor memory, has delay locked loop circuit which receives offset code from up-down counter, and generates pair of clock signals having different phase differences
03/17/2005DE102004015575A1 Verfahren, Vorrichtung und System zum Löschen und Schreiben eines magnetischen Direktzugriffsspeichers Method, apparatus and system for erasing and writing a magnetic random access memory
03/17/2005DE10037988B4 Vorrichtung und Verfahren zum Testen von Halbleiterspeichern Apparatus and method for testing semiconductor memories
03/16/2005EP1515345A1 Test method and test circuit for electronic device
03/16/2005EP1515343A2 Semiconductor memory device
03/16/2005EP1514277A1 Ram memory circuit with several banks and an auxiliary device for testing
03/16/2005EP1390951B1 Dynamic memory and method for testing a dynamic memory
03/16/2005EP1323167B1 A method for performing write and read operations in a passive matrix memory, and apparatus for performing the method
03/16/2005CN1595807A Semiconductor integrated circuit in which voltage down converter output can be observed as digital value
03/16/2005CN1595537A A system for simulating physical damage of NAND flash memory and method thereof
03/16/2005CN1595536A Reliable storage method for financial tax control data
03/16/2005CN1193376C Semiconductor integrated circuit and its storage repairing method
03/15/2005US6868047 Compact ATE with time stamp system
03/15/2005US6868034 Circuits and methods for changing page length in a semiconductor memory device
03/15/2005US6868032 Nonvolatile memory
03/15/2005US6868022 Redundant memory structure using bad bit pointers
03/15/2005US6868021 Rapidly testable semiconductor memory device
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