Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
03/2005
03/15/2005US6868020 Synchronous semiconductor memory device having a desired-speed test mode
03/15/2005US6868019 Reduced power redundancy address decoder and comparison circuit
03/15/2005US6868008 Non-volatile semiconductor memory device
03/15/2005US6867993 Semiconductor memory device
03/15/2005US6867055 Method of testing ion implantation energy in ion implantation equipment
03/10/2005US20050055621 Magnetic memory with error correction coding
03/10/2005US20050055610 Storage device, data processing system and data writing and readout method
03/10/2005US20050055497 Faster write operations to nonvolatile memory by manipulation of frequently-accessed sectors
03/10/2005US20050055173 Self-test architecture to implement data column redundancy in a RAM
03/10/2005US20050052933 [device and method for breaking leakage current path]
03/10/2005US20050052930 Semiconductor memory device including page latch circuit
03/10/2005US20050052928 Semiconductor memory device and method for manufacturing same
03/10/2005US20050052915 Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states
03/10/2005US20050052911 Semiconductor device having a redundant memory cell and method for recovering the same
03/10/2005US20050052906 Row decoder in flash memory and erase method of flash memory cell using the same
03/10/2005US20050052895 FeRAM using programmable register
03/10/2005US20050052307 Semiconductor integrated circuit in which voltage down converter output can be observed as digital value and voltage down converter output voltage is adjustable
03/10/2005US20050052218 Fuse latch circuit with non-disruptive re-interrogation
03/10/2005US20050051841 Stress-controlled dielectric integrated circuit
03/10/2005US20050051765 Test structure for a single-sided buried strap DRAM memory cell array
03/09/2005EP0725324B1 Methods for avoiding overcommitment of virtual capacity in a redundant hierarchic data storage system
03/09/2005CN1591697A Method and apparatus for checking IC output signal
03/09/2005CN1591696A 半导体集成电路 The semiconductor integrated circuit
03/09/2005CN1591695A Test structure for a single-sided buried strap dram memory cell data array
03/09/2005CN1591694A Apparatus and method for testing semiconductor memory devices
03/09/2005CN1591693A Flash memory with pre-detection for data loss
03/09/2005CN1591689A Nonvolatile semiconductor memory device
03/09/2005CN1591671A Semiconductor integrated circuit device and error detecting method therefor
03/09/2005CN1192412C Fuse latch circuit
03/09/2005CN1192393C Semiconductor memory device incorporating redundancy memory cells having uniform layout
03/09/2005CN1192242C Lead frame structure for testing integrated circuits
03/08/2005US6865707 Test data generator
03/08/2005US6865705 Semiconductor integrated circuit device capable of switching mode for trimming internal circuitry through JTAG boundary scan method
03/08/2005US6865702 Synchronous flash memory with test code input
03/08/2005US6865701 Method and apparatus for improved memory core testing
03/08/2005US6865698 Method and apparatus for testing semiconductor devices
03/08/2005US6865694 CPU-based system and method for testing embedded memory
03/08/2005US6865660 Method and apparatus for generating deterministic, non-repeating, pseudo-random addresses
03/08/2005US6865133 Memory circuit with redundant configuration
03/08/2005US6865126 Semiconductor memory device capable of relieving defective cell
03/08/2005US6865125 Non-volatile semiconductor memory
03/08/2005US6865124 Semiconductor device with flexible redundancy system
03/08/2005US6865123 Semiconductor memory device with enhanced repair efficiency
03/08/2005US6865111 Method and architecture to calibrate read operations in synchronous flash memory
03/08/2005US6865104 Magnetoresistive random access memory (MRAM) with on-chip automatic determination of optimized write current method and apparatus
03/08/2005US6865103 Thin film magnetic memory device having a redundant structure
03/08/2005US6864693 Semiconductor integrated circuit with negative voltage generation circuit, test method for the same, and recording device and communication equipment having the same
03/08/2005US6864106 Method and system for detecting tunnel oxide encroachment on a memory device
03/03/2005US20050050421 Semiconductor integrated circuit device and error detecting method therefor
03/03/2005US20050050411 Pre-stored digital word generator
03/03/2005US20050050410 Memory error ranking
03/03/2005US20050050409 Apparatus and method for testing semiconductor memory devices, capable of selectively changing frequencies of test pattern signals
03/03/2005US20050050408 Apparatus and methods for testing memory devices
03/03/2005US20050050399 Field spike monitor for MRAM
03/03/2005US20050050276 System and method for testing a memory
03/03/2005US20050049810 Method and system for determining minimum post production test time required on an integrated circuit device to achieve optimum reliability
03/03/2005US20050047260 Semiconductor integrated circuit
03/03/2005US20050047253 Sharing fuse blocks between memories in hard-bisr
03/03/2005US20050047232 Semiconductor integrated circuit device
03/03/2005US20050047229 Method and circuit for collecting memory failure information
03/03/2005US20050047228 Method and system for selecting redundant rows and columns of memory cells
03/03/2005US20050047226 Redundancy scheme for a memory integrated circuit
03/03/2005US20050047225 Semiconductor memory device
03/03/2005US20050047221 Negative drop voltage generator in semiconductor memory device and method of controlling negative voltage generation
03/03/2005US20050047202 Magnetic random access memory having test circuit and test method therefor
03/03/2005US20050047190 FeRAM having test circuit and method for testing the same
03/03/2005US20050046426 Simulated module load
03/03/2005DE10316931B4 Verfahren und Vorrichtung zum Testen von DRAM-Speicherbausteinen in Multichip-Speichermodulen Method and device for testing of DRAM memory devices in memory modules, multichip
03/02/2005EP1509924A1 Semiconductor memory device with test mode to monitor internal timing control signals at i/o terminals
03/02/2005EP1509921A2 Content addressable memory (cam) with error checking and correction
03/02/2005EP1242999B1 Usage of redundancy data for displaying failure bit maps for semiconductor devices
03/02/2005EP0926687B1 Self-test and correction of loss of charge errors in a flash memory, erasable and programmable by sectors thereof
03/02/2005CN1191585C Self-analyzing semiconductor IC unit capable of carrying out redundant replacement with installed memory circrits
03/01/2005US6862721 Method for identification of faulty or weak functional logic elements under simulated extreme operating conditions
03/01/2005US6862704 Apparatus and method for testing memory in a microprocessor
03/01/2005US6862703 Apparatus for testing memories with redundant storage elements
03/01/2005US6862702 Address counter for addressing synchronous high-frequency digital circuits, in particular memory devices
03/01/2005US6862700 Memory redundancy with programmable non-volatile control
03/01/2005US6862247 Pseudo-static synchronous semiconductor memory device
03/01/2005US6862243 Flash array implementation with local and global bit lines
03/01/2005US6862240 Variable refresh control for a memory
03/01/2005US6862234 Method and test circuit for testing a dynamic memory circuit
03/01/2005US6862233 Method and circuit for determining sense amplifier sensitivity
03/01/2005US6862231 Repair circuit
03/01/2005US6862230 Efficient column redundancy techniques
03/01/2005US6862227 Semiconductor memory device having the operating voltage of the memory cell controlled
03/01/2005US6861866 System on chip (SOC) and method of testing and/or debugging the system on chip
03/01/2005US6861682 Laser link structure capable of preventing an upper crack and broadening an energy window of a laser beam, and fuse box using the same
02/2005
02/24/2005WO2005017959A2 Integrated circuit with test pad structure and method of testing
02/24/2005WO2005017915A1 Storage device and method for testing storage device
02/24/2005WO2005017914A1 Semiconductor memory and operation method of semiconductor memory
02/24/2005WO2005017913A1 Reduced power consumption in integrated circuits with fuse controlled redundant circuits
02/24/2005WO2004114319A3 Apparatus and method for testing memory cards
02/24/2005US20050044462 Apparatus and method for testing circuit units to be tested
02/24/2005US20050044459 Redundant memory structure using bad bit pointers
02/24/2005US20050044458 Testing board for semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory
02/24/2005US20050044457 System and method for on-board diagnostics of memory modules
02/24/2005US20050044456 Method for testing media in a library without inserting media into the library database
02/24/2005US20050044441 Memory device for compensating for a clock skew causing a centering error and a method of compensating for the clock skew
02/24/2005US20050044303 Memory system including an integrated circuit buffer device
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