Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
05/2005
05/25/2005CN1203487C Semiconductor memory
05/24/2005US6898745 Integrated device with operativity testing
05/24/2005US6898739 Method and device for testing a memory circuit
05/24/2005US6898538 Method and system for the adjustment of an internal timing signal or a corresponding reference in an integrated circuit, and corresponding integrated circuit
05/24/2005US6898145 Distributed, highly configurable modular predecoding
05/24/2005US6898143 Sharing fuse blocks between memories in hard-BISR
05/24/2005US6898139 Integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation
05/24/2005US6898133 Package map data outputting circuit of semiconductor memory device and method for outputting package map data
05/24/2005US6898119 Nonvolatile semiconductor memory and its test method
05/24/2005US6898117 Multi-bit-per-cell flash EEPROM memory with refresh
05/24/2005US6898113 Magnetic memory device with reference cell for data reading
05/24/2005US6898110 Semiconductor integrated circuit device
05/19/2005WO2005045845A1 Refresh for dynamic cells with weak retention
05/19/2005WO2005045373A1 Memory device, memory control method and display device
05/19/2005WO2004095461A3 Redundant memory structure using bad bit pointers
05/19/2005US20050108613 Disk array device, parity data generating circuit for raid and galois field multiplying circuit
05/19/2005US20050108609 Method for testing circuit units to be tested by means of majority decisions and test device for performing the method
05/19/2005US20050108607 Semiconductor memory device and test pattern data generating method using the same
05/19/2005US20050108606 Input/output switching arrangement for semiconductor circuits, a method for testing driver circuits in semiconductor circuits
05/19/2005US20050108603 Input switching arrangement for a semiconductor circuit and test method for unidirectional input drivers in semiconductor circuits
05/19/2005US20050108602 Methodology for performing register read/writes to two or more expanders with a common test port
05/19/2005US20050108491 Method for testing flash memory power loss recovery
05/19/2005US20050108458 Lane testing with variable mapping
05/19/2005US20050107987 System and method for testing a memory with an expansion card using DMA
05/19/2005US20050107262 Information recording method using superconduction having bands, calculating method, information transmitting method, energy storing method, magnetic flux measuring method, and quantum bit construction method
05/19/2005US20050106359 Method of processing substrate
05/19/2005US20050105365 Repair fuse box of semiconductor device
05/19/2005US20050105350 Memory channel test fixture and method
05/19/2005US20050105345 Pulse width adjusting circuit for use in semiconductor memory device and method therefor
05/19/2005US20050105333 Method of measuring threshold voltage for a NAND flash memory device
05/19/2005US20050105316 Multi chip package type memory system and a replacement method of replacing a defect therein
05/19/2005US20050105315 Content addressable memory (CAM) capable of finding errors in a CAM cell array and a method thereof
05/19/2005US20050104612 Current mirror multi-channel leakage current monitor circuit and method
05/19/2005US20050104103 Nonvolatile semiconductor memory device including high efficiency and low cost redundant structure
05/19/2005US20050104063 Shallow trench isolation void detecting method and structure for the same
05/18/2005EP1402278A4 Method and apparatus for optimized parallel testing and access of electronic circuits
05/18/2005CN1618027A Compact ate with timestamp system
05/18/2005CN1617335A Repair fuse box of semiconductor device
05/18/2005CN1617262A Method for detecting FCASH inner unit
05/18/2005CN1617260A Encoding circuit for semiconductor device and redundancy control circuit using the same
05/17/2005US6895538 Method for testing a device and a test configuration including a device with a test memory
05/17/2005US6895537 Semiconductor integrated circuit device including semiconductor memory with tester circuit capable of analyzing redundancy repair
05/17/2005US6894945 Clock synchronous semiconductor memory device
05/17/2005US6894944 Semiconductor integrated circuit device
05/17/2005US6894938 System and method of calibrating a read circuit in a magnetic memory
05/17/2005US6894937 Accelerated life test of MRAM cells
05/17/2005US6894922 Memory device capable of performing high speed reading while realizing redundancy replacement
05/17/2005US6894526 Apparatus for determining burn-in reliability from wafer level burn-in
05/17/2005US6894517 Method for monitoring oxide quality
05/12/2005WO2005043276A2 System-in-package and method of testing thereof
05/12/2005WO2004090723A3 A high reliability memory module with a fault tolerant address and command bus
05/12/2005US20050102603 In-service raid mirror reconfiguring
05/12/2005US20050102602 DVD EDC check system and method without descrambling sector data
05/12/2005US20050102595 Method and apparatus for testing semiconductor memory device and related testing methods
05/12/2005US20050102591 Failure detection system, failure detection method, and computer program product
05/12/2005US20050102590 Method for performing a burn-in test
05/12/2005US20050102589 Flash memory test system and method capable of test time reduction
05/12/2005US20050102581 Active compensation for operating point drift in MRAM write operation
05/12/2005US20050102577 Method and circuitry for debugging/updating ROM
05/12/2005US20050102576 Multi-sample read circuit having test mode of operation
05/12/2005US20050099881 Apparatus for interleave and method thereof
05/12/2005US20050099879 Circuit arrangement for reading out, evaluating and reading in again a charge state into a memory cell
05/12/2005US20050099875 Method and apparatus for redundant location addressing using data compression
05/12/2005US20050099868 Refresh for dynamic cells with weak retention
05/12/2005US20050099866 Method and circuit for determining sense amplifier sensitivity
05/12/2005US20050099861 Reduced power redundancy address decoder and comparison circuit
05/12/2005US20050099858 Encoding circuit for semiconductor device and redundancy control circuit using the same
05/12/2005US20050099855 System and method for determining the logic state of a memory cell in a magnetic tunnel junction memory device
05/12/2005US20050099852 Circuit calibrating output driving strength of DRAM and method thereof
05/12/2005US20050099837 Semiconductor memory device for controlling write recovery time
05/12/2005US20050099832 System and method for securing an integrated circuit as against subsequent reprogramming
05/12/2005US20050099202 Method of testing an integrated circuit and an integrated circuit test apparatus
05/12/2005US20050098881 Memory module and method for operating a memory module
05/12/2005US20050098800 Nonvolatile memory cell comprising a reduced height vertical diode
05/12/2005DE19708441B4 Verfahren zum Schreiben und Lesen von für den Betrieb einer Fahrzeugkomponente relevanten Betriebsparametern in einen bzw. aus einem Schreib/Lese-Speicher A method of writing and reading of relevant for the operation of a vehicle component operating parameters in and out of a read / write memory
05/11/2005EP1529293A1 Built-in-self-test of flash memory cells
05/11/2005EP1425665B1 Method and device for testing a memory
05/11/2005CN1614717A Method of detecting errors in a priority encoder and a content addressable memory adopting the same
05/11/2005CN1201398C Semiconductor chip with fuse element and semiconductor module
05/11/2005CN1201332C Semiconductor memory and method for replacing faitured unit therein
05/10/2005US6892328 Method and system for distributed testing of electronic devices
05/10/2005US6892318 Method for repairing a semiconductor memory
05/10/2005US6891774 Delay line and output clock generator using same
05/10/2005US6891766 Semiconductor memory test device
05/10/2005US6891765 Circuit and/or method for implementing a patch mechanism for embedded program ROM
05/10/2005US6891743 Semiconductor memory device having a capacitive plate to reduce soft errors
05/10/2005US6891404 Auto-adjustment of self-refresh frequency
05/10/2005US6891393 Synchronous semiconductor device, and inspection system and method for the same
05/10/2005US6891387 System for probing, testing, burn-in, repairing and programming of integrated circuits
05/06/2005WO2005041293A1 Backside of chip implementation of redundancy fuses and contact pads
05/06/2005WO2005041107A2 A method circuit and system for determining a reference voltage
05/06/2005WO2005040951A1 Voltage trimming circuit
05/05/2005US20050097418 Semiconductor integrated circuit
05/05/2005US20050097417 Novel bisr mode to test the redundant elements and regular functional memory to avoid test escapes
05/05/2005US20050097412 Synchronous flash memory with test code input
05/05/2005US20050097411 System and method for verifying data integrity
05/05/2005US20050097410 Memory device and input signal control method of a memory device
05/05/2005US20050097383 New hard BISR scheme allowing field repair and usage of reliability controller
05/05/2005US20050097377 Power-saving control circuitry of electronic device and operating method thereof
05/05/2005US20050096876 Semiconductor test apparatus and method thereof and multiplexer and method thereof
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