Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
06/2005
06/23/2005US20050138506 Apparatus for testing a memory module
06/23/2005US20050138502 Test mode circuit of semiconductor device
06/23/2005US20050138501 System and method for testing electronic devices on a microchip
06/23/2005US20050138497 Apparatus and method for testing a flash memory unit
06/23/2005US20050138496 Method and apparatus for test and repair of marginally functional SRAM cells
06/23/2005US20050138495 Magnetic memory which compares compressed fault maps
06/23/2005US20050138491 Circuit arrangement and method for driving electronic chips
06/23/2005US20050138302 Method and apparatus for logic analyzer observability of buffered memory module links
06/23/2005US20050135171 Method and apparatus for controlling refresh cycles of a plural cycle refresh scheme in a dynamic memory
06/23/2005US20050135167 Memory access circuit for adjusting delay of internal clock signal used for memory control
06/23/2005US20050135165 MRAM with controller
06/23/2005US20050135163 Integrated circuit for storing operating parameters
06/23/2005US20050135142 Storage circuit, semiconductor device, electronic apparatus, and driving method
06/23/2005US20050134340 Data strobe circuit using clock signal
06/23/2005US20050134250 Power detector for use in a nonvolatile memory device and method thereof
06/23/2005US20050133822 Apparatus for pulse testing a MRAM device and method therefore
06/23/2005DE19851861B4 Fehleranalysespeicher für Halbleiterspeicher-Testvorrichtungen und Speicherverfahren unter Verwendung des Fehleranalysespeichers Failure analysis memory for semiconductor memory devices and memory test method using the failure analysis memory
06/22/2005EP1544741A1 Defect tolerant circuit with redundancy
06/22/2005EP1543528A2 Acceleration of the programming of a memory module with the aid of a boundary scan (bscan) register
06/22/2005EP1543526A2 Method of recovering overerased bits in a memory device
06/22/2005EP1543506A1 Write-once type optical disc, and method and apparatus for managing defective areas on write-once type optical disc
06/22/2005CN1630054A Semiconductor device testing apparatus, system, and method for testing the contacting with semiconductor devices positioned one upon the other
06/22/2005CN1629978A Storage circuit, semiconductor device, electronic apparatus, and driving method
06/22/2005CN1207720C Semiconductor memory device
06/21/2005US6910164 High-resistance contact detection test mode
06/21/2005US6910163 Method and configuration for the output of bit error tables from semiconductor devices
06/21/2005US6910162 Memory-module burn-in system with removable pattern-generator boards separated from heat chamber by backplane
06/21/2005US6910161 Device and method for reducing the number of addresses of faulty memory cells
06/21/2005US6910155 System and method for chip testing
06/21/2005US6910152 Device and method for repairing a semiconductor memory
06/21/2005US6909653 Memory integrated circuit device having self reset circuit for precharging data buses based on the detection of their discharge levels
06/21/2005US6909651 Method and apparatus for testing a CAM addressed cache
06/21/2005US6909650 Circuit and method for transforming data input/output format in parallel bit test
06/21/2005US6909649 Semiconductor device and semiconductor integrated circuit
06/21/2005US6909648 Burn in system and method for improved memory reliability
06/21/2005US6909647 Semiconductor device having redundancy circuit
06/21/2005US6909646 Semiconductor memory device having improved arrangement for replacing failed bit lines
06/21/2005US6909645 Cluster based redundancy scheme for semiconductor memories
06/21/2005US6909642 Self trimming voltage generator
06/21/2005US6909641 Flash memory sector tagging for consecutive sector erase or bank erase
06/21/2005US6909640 Block select circuit in a flash memory device
06/21/2005US6909636 Flash array implementation with local and global bit lines
06/21/2005US6909635 Programmable memory cell using charge trapping in a gate oxide
06/21/2005US6909629 MRAM signal size increasing apparatus and methods
06/21/2005US6909624 Semiconductor memory device and test method thereof
06/21/2005US6909387 Circuit, apparatus and method for improved current distribution of output drivers enabling improved calibration efficiency and accuracy
06/21/2005US6909315 Data strobe signals (DQS) for high speed dynamic random access memories (DRAMs)
06/21/2005US6909301 Oscillation based access time measurement
06/16/2005WO2005006394A3 Circuit for testing and fine tuning integrated circuit (switch control circuit)
06/16/2005US20050132263 Memory error detection reporting
06/16/2005US20050132255 Low-power SRAM E-fuse repair methodology
06/16/2005US20050130351 Methods for maskless lithography
06/16/2005US20050128859 Delay circuit, ferroelectric memory device and electronic equipment
06/16/2005US20050128854 Synchronous controlled, self-timed local SRAM block
06/16/2005US20050128837 Random access memory using precharge timers in test mode
06/16/2005US20050128833 Semiconductor memory device having access time control circuit
06/16/2005US20050128832 Method of determining localized electron tunneling in a capacitive structure
06/16/2005US20050128830 Semiconductor memory device
06/16/2005US20050128823 Methods and apparatus for improved memory access
06/16/2005US20050128820 Circuit for detecting negative word line voltage
06/16/2005US20050128789 SRAM device and a method of operating the same to reduce leakage current during a sleep mode
06/16/2005US20050127985 Semiconductor device having logic circuit and macro circuit
06/16/2005DE10345976A1 Test device for testing a circuit unit applies a test system, a register device for storing initializing data, a control unit and a switch-on unit
06/16/2005DE102004032466A1 Mehrfachabtastleseschaltung mit Testbetriebsmodus Mehrfachabtastleseschaltung with test mode
06/16/2005DE102004012487A1 Strom sparende Steuerschaltung einer elektronischen Vorrichtung und Betriebsverfahren davon Power saving control circuit of an electronic device and driving method thereof
06/15/2005EP1542237A1 Semiconductor memory
06/15/2005EP1542236A2 Apparatus and method of analyzing magnetic random access memory
06/15/2005EP1540660A2 Method of and apparatus for detecting an error in writing to persistent memory
06/15/2005EP1540510A1 Method and apparatus for managing data integrity of backup and disaster recovery data
06/15/2005EP1540478A1 Primary and remote data backup with nodal failover
06/15/2005EP1540441A2 Method and apparatus for server share migration and server recovery using hierarchical storage management
06/15/2005CN1627516A Test module and test method in use for electrical erasable memory built in chip
06/15/2005CN1627475A Fabricating of integrated memory modular
06/15/2005CN1627445A Delay circuit, ferroelectric memory device and electronic equipment
06/15/2005CN1627426A Error corrector and its method
06/15/2005CN1206733C Semiconductor integrated circuit
06/15/2005CN1206659C Method of testing memory
06/15/2005CN1206658C Semiconductor device
06/15/2005CN1206657C Flash memory
06/15/2005CN1206655C Read amplifier
06/14/2005US6907555 Self-test circuit and memory device incorporating it
06/14/2005US6907554 Built-in self test system and method for two-dimensional memory redundancy allocation
06/14/2005US6907544 Method for operating memory devices for storing data
06/14/2005US6907385 Memory defect redress analysis treating method, and memory testing apparatus performing the method
06/14/2005US6906970 Address counter strobe test mode device
06/14/2005US6906969 Hybrid fuses for redundancy
06/14/2005US6906968 Input buffer of semiconductor memory device
06/14/2005US6906967 Negative drop voltage generator in semiconductor memory device and method of controlling negative voltage generation
06/14/2005US6906943 Ferroelectric memory device comprising extended memory unit
06/09/2005WO2005052611A1 Identifying process and temperature of silicon chips
06/09/2005WO2005027134A3 Multiple bit chalcogenide storage device
06/09/2005US20050125712 Manifold-Distributed Air Flow Over Removable Test Boards in a Memory-Module Burn-In System With Heat Chamber Isolated by Backplane
06/09/2005US20050125595 Non-volatile semiconductor memory
06/09/2005US20050122832 On-die detection of the system operation frequency in a DRAM to adjust DRAM operations
06/09/2005US20050122831 Method and architecture to calibrate read operations in synchronous flash memory
06/09/2005US20050122822 Random access memory with optional inaccessible memory cells
06/09/2005US20050122805 Burn in system and method for improved memory reliability
06/09/2005US20050122804 Shift redundancy circuit, method for controlling shift redundancy circuit, and semiconductor memory device
06/09/2005US20050122802 Semiconductor storage device formed to optimize test technique and redundancy technology
06/09/2005US20050122801 Flexible row redundancy system
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