| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 07/12/2005 | US6917208 Method and test structure for determining resistances at a plurality of interconnected resistors in an integrated circuit |
| 07/07/2005 | WO2005062311A1 Semiconductor device |
| 07/07/2005 | US20050149828 Digital signal forming method, disc recording media using the same, and reproducing method thereof |
| 07/07/2005 | US20050149826 Data recording and reproducing system, and data recording and reproducing method |
| 07/07/2005 | US20050149824 Method for fast ECC memory testing by software including ECC check byte |
| 07/07/2005 | US20050149803 Semiconductor testing equipment, testing method for semiconductor, fabrication method of semiconductor, and semiconductor memory |
| 07/07/2005 | US20050149794 Memory circuit having a controllable output drive |
| 07/07/2005 | US20050149792 Semiconductor device and method for testing the same |
| 07/07/2005 | US20050149788 Methods of testing semiconductor memory devices in a variable CAS latency environment and related semiconductor test devices |
| 07/07/2005 | US20050149786 Apparatus and method for determining threshold voltages in a flash memory unit |
| 07/07/2005 | US20050149785 Apparatus and method for testing a flash memory unit using stress voltages |
| 07/07/2005 | US20050149782 Semiconductor memory repair methodology using quasi-non-volatile memory |
| 07/07/2005 | US20050149781 System and method for soft error handling |
| 07/07/2005 | US20050149780 System-in-package and method of testing thereof |
| 07/07/2005 | US20050149687 Device identification using a memory profile |
| 07/07/2005 | US20050149662 System having a plurality of integrated circuit buffer devices |
| 07/07/2005 | US20050149591 Method and apparatus for generating deterministic, non-repeating, pseudo-random addresses |
| 07/07/2005 | US20050149285 Method of and system for analyzing cells of a memory device |
| 07/07/2005 | US20050147008 Method for creating defect management information in an recording medium, and apparatus and medium based on said method |
| 07/07/2005 | US20050146981 Apparatus for testing a nonvolatile memory and a method thereof |
| 07/07/2005 | US20050146970 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used |
| 07/07/2005 | US20050146969 Semiconductor memory apparatus |
| 07/07/2005 | US20050146968 Semiconductor memory |
| 07/07/2005 | US20050146959 Non-volatile semiconductor memory device and electric device with the same |
| 07/07/2005 | US20050146952 Memory circuit with shared redundancy |
| 07/07/2005 | US20050146924 Semiconductor integrated circuit and method for detecting soft defects in static memory cell |
| 07/07/2005 | US20050146920 Access circuit and method for allowing external test voltage to be applied to isolated wells |
| 07/07/2005 | US20050146915 Storage circuit, semiconductor device, and electronic apparatus |
| 07/07/2005 | US20050146914 Storage circuit, semiconductor device, and electronic apparatus |
| 07/07/2005 | US20050146910 Method and apparatus for reconfigurable memory |
| 07/07/2005 | US20050146373 Fuse circuit |
| 07/07/2005 | DE102004040484A1 Auswählen eines Schreibstroms einer magnetischen Speicherzelle Selecting a write current to a magnetic memory cell |
| 07/07/2005 | DE102004037834A1 Speichervorrichtung Memory device |
| 07/06/2005 | EP1026696B1 Test method and test circuit for electronic device |
| 07/06/2005 | CN1636260A Semiconductor memory having segmented row repair |
| 07/06/2005 | CN1636250A Fuse concept and method of operation |
| 07/06/2005 | CN1209817C Refractory fuse circuit for packaged DRAM repair |
| 07/06/2005 | CN1209767C Circuit for evaluating information content of memory cell |
| 07/05/2005 | US6915476 Redundancy semiconductor memory device with error correction code (ECC) circuits for correcting errors in recovery fuse data |
| 07/05/2005 | US6915469 High speed vector access method from pattern memory for test systems |
| 07/05/2005 | US6915468 Apparatus for testing computer memory |
| 07/05/2005 | US6915467 System and method for testing a column redundancy of an integrated circuit memory |
| 07/05/2005 | US6914846 Flash EEprom system |
| 07/05/2005 | US6914843 Memory device tester and method for testing reduced power states |
| 07/05/2005 | US6914842 Pure CMOS latch-type fuse circuit |
| 07/05/2005 | US6914834 System and method for the functional testing of semiconductor memory chips |
| 07/05/2005 | US6914833 Apparatus for random access memory array self-repair |
| 07/05/2005 | US6914832 Semiconductor memory device with memory cell array divided into blocks |
| 07/05/2005 | US6914817 Highly compact EPROM and flash EEPROM devices |
| 07/05/2005 | US6914814 Dedicated redundancy circuits for different operations in a flash memory device and methods of operating the same |
| 07/05/2005 | US6914799 Semiconductor memory device |
| 07/05/2005 | US6914447 High activity, spatially distributed radiation source for accurately simulating semiconductor device radiation environments |
| 07/05/2005 | CA2194341C Apparatus and method for detecting and assessing a spatially discrete dot pattern |
| 06/30/2005 | US20050144551 MRAM having error correction code circuitry and method therefor |
| 06/30/2005 | US20050144516 Adaptive deterministic grouping of blocks into multi-block units |
| 06/30/2005 | US20050144365 Non-volatile memory and method with control data management |
| 06/30/2005 | US20050144360 Non-volatile memory and method with block management system |
| 06/30/2005 | US20050141387 Flexible and area efficient column redundancy for non-volatile memories |
| 06/30/2005 | US20050141336 Method for producing an integrated memory module |
| 06/30/2005 | US20050141334 Circuit and method for controlling inversion of delay locked loop and delay locked loop and synchronous semiconductor memory device using the same |
| 06/30/2005 | US20050141332 Semiconductor device including a register to store a value that is representative of device type information |
| 06/30/2005 | US20050141325 Efficent column redundancy techniques |
| 06/30/2005 | US20050141314 Semiconductor integrated circuit device and digital measuring instrument |
| 06/30/2005 | US20050141313 Non-volatile memory and method with memory planes alignment |
| 06/30/2005 | US20050141312 Non-volatile memory and method with non-sequential update block management |
| 06/30/2005 | US20050141305 Memory redundancy with programmable control |
| 06/30/2005 | US20050141304 Memory redundancy with programmable non-volatile control |
| 06/30/2005 | US20050141303 Look-up table for use with redundant memory |
| 06/30/2005 | US20050141302 Method for surveying layout of information devices |
| 06/30/2005 | US20050141301 Semiconductor device and method of controlling the semiconductor device |
| 06/30/2005 | US20050141300 Nonvolatile memory |
| 06/30/2005 | US20050141299 Semiconductor memory device for controlling cell block with state machine |
| 06/30/2005 | US20050141297 Semiconductor memory device of bit line twist system |
| 06/30/2005 | US20050141289 Semiconductor memory device having the operating voltage of the memory cell controlled |
| 06/30/2005 | US20050141264 Semiconductor device |
| 06/30/2005 | US20050140403 Internal clock doubler |
| 06/30/2005 | DE10357862B3 Verfahren zur Herstellung eines integrierten Speicherbausteins A method for manufacturing an integrated memory device |
| 06/30/2005 | DE10356359A1 Semiconductor memory analyzing method, involves compressing comparison bit sequence, such that sequence bits are linked with logic operation, and stopping production and display of parity bit for relative cell in one operation mode |
| 06/30/2005 | DE10354112A1 Repair method for memory chips uses redundant cell areas and corresponding fuses with micro-lithographic devices |
| 06/30/2005 | DE10353586A1 Ein/Ausgangschaltanordnung für Halbleiterschaltungen und Verfahren zur Prüfung von Treiberschaltkreisen von Halbleiterschaltungen Input / output circuitry for semiconductor circuits and methods for testing driver circuits of semiconductor circuits |
| 06/30/2005 | DE10353585A1 Unidirektionale Eingangsschaltanordnung, Halbleiterschaltung und Verfahren zur Prüfung einer Laufzeitverzögerung eines Eingangstreibers einer Halbleiterschaltung Unidirectional input circuitry, semiconductor circuit and method for testing a propagation delay of an input driver of a semiconductor circuit |
| 06/30/2005 | DE102004048652A1 Halbleiterspeicherbaustein und Verfahren zu dessen Herstellung Semiconductor memory device and method for its production |
| 06/30/2005 | DE102004010244A1 High leakage current trench capacitor cells detecting method for use in dynamic RAM, involves comparing measure of leakage current of capacitor cells to recognize those cells having high leakage current |
| 06/29/2005 | EP1548599A2 Faster write operations to nonvolatile memory by manipulation of frequently accessed sectors |
| 06/29/2005 | EP1547094A1 Method and circuitry for identifying weak bits in an mram |
| 06/29/2005 | EP1547093A2 Sensing test circuit |
| 06/28/2005 | US6912680 Memory system with dynamic timing correction |
| 06/28/2005 | US6912677 Circuit for inspecting a data error |
| 06/28/2005 | US6912665 Automatic timing analyzer |
| 06/28/2005 | US6912618 Direct logical block addressing flash memory mass storage architecture |
| 06/28/2005 | US6912172 Semiconductor device and method of the semiconductor device |
| 06/28/2005 | US6912170 Method and apparatus for permanent electrical removal of an integrated circuit output after packaging |
| 06/28/2005 | US6912166 Semiconductor memory device and test method thereof |
| 06/28/2005 | US6912150 Reference current generator, and method of programming, adjusting and/or operating same |
| 06/28/2005 | CA2222665C Graphical editor for defining memory test sequences |
| 06/23/2005 | WO2005057412A1 Data storage system with error correction code and replaceable defective memory |
| 06/23/2005 | US20050138537 Method and system to encode and decode wide data words |
| 06/23/2005 | US20050138526 Recovering track format information mismatch errors using data reconstruction |
| 06/23/2005 | US20050138525 System and method for forward error correction |
| 06/23/2005 | US20050138513 Multiple on-chip test runs and repairs for memories |