Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
08/2005
08/30/2005US6937526 Memory card enabling simplified test process and memory card test method
08/30/2005US6937512 Nonvolatile semiconductor memory device with a ROM block settable in the write or erase inhibit mode
08/30/2005US6937504 Selecting a magnetic memory cell write current
08/30/2005US6937493 Programming flash memory via a boundary scan register
08/30/2005US6937087 Temperature sensor and method for detecting trip temperature of a temperature sensor
08/30/2005US6937051 Integrated circuit that can be externally tested through a normal signal output pin
08/30/2005US6937048 Method for testing an integrated circuit with an external potential applied to a signal output pin
08/30/2005US6937047 Integrated circuit with test pad structure and method of testing
08/30/2005US6936889 Semiconductor device and method for testing semiconductor device
08/25/2005WO2005078769A2 Manufacturing integrated circuits
08/25/2005WO2005078736A1 Semiconductor device testing apparatus and testing method
08/25/2005WO2005078735A1 Semiconductor memory
08/25/2005WO2005078734A1 Dll circuit
08/25/2005WO2005077024A2 Methods and apparatus for data analysis
08/25/2005WO2004104840A3 Memory with bit swapping on the fly and testing
08/25/2005US20050188292 Method and apparatus for encoding special uncorrectable errors in an error correction code
08/25/2005US20050188288 System and method for accelerated information handling system memory testing
08/25/2005US20050188287 Testing and repair methodology for memories having redundancy
08/25/2005US20050188286 Method for determining integrity of memory
08/25/2005US20050188255 Custom logic BIST for memory controller
08/25/2005US20050188147 Non-volatile semiconductor memory system
08/25/2005US20050186934 Semiconductor integrated circuit
08/25/2005US20050186326 High activity, spatially distributed radiation source for accurately simulating semiconductor device radiation environments
08/25/2005US20050185495 Semiconductor memory device having a single input terminal to select a buffer and method of testing the same
08/25/2005US20050185485 Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device
08/25/2005US20050185484 Semiconductor memory device having test mode for data access time
08/25/2005US20050185483 Semiconductor memory storage device and its redundant method
08/25/2005US20050185482 Semiconductor memory storage device and a redundancy control method therefor
08/25/2005US20050185481 Redundancy relieving circuit
08/25/2005US20050185479 Method and device for saving and setting a circuit state of a microelectronic circuit
08/25/2005US20050185473 Memory cell testing feature
08/25/2005US20050184896 Circuit, apparatus and method for improved current distribution of output drivers enabling improved calibration efficiency and accuracy
08/25/2005US20050184289 Device and method for detecting alignment of active areas and memory cell structures in dram devices
08/25/2005DE69233384T2 Nicht-flüchtiger Halbleiterspeicher A non-volatile semiconductor memory
08/25/2005DE10393447T5 Mehrabtastsignal-Gerät, Testgerät und Einstellverfahren Mehrabtastsignal equipment, test equipment and setting
08/25/2005DE10260184B4 Speichermodul mit einer Testeinrichtung Memory module with a test device
08/25/2005DE102004063571A1 System und Verfahren zum Konfigurieren einer Festkörperspeicherungsvorrichtung mit Fehlerkorrekturcodierung System and method for configuring a solid state storage device with error correction coding
08/25/2005DE102004004808A1 Maintenance of the state of a microelectronic circuit, in which certain circuit sections can be turned off, whereby a scan chain used for circuit testing is also used to collect register contents and then shift them into memory
08/25/2005DE102004004562A1 Memory device with redundant memory management has a reserve memory cell field and a memory control unit that reallocates defective main memory cells to reserve memory cells
08/25/2005DE10146084B4 Verfahren zum schnellen Schreiben eines vorgegebenen Datenmusters in eine als Speicherbaustein ausgebildete integrierte Schaltung sowie Speicherschaltung Method for rapid writing a predetermined data pattern into a memory device configured as integrated circuit and memory circuit
08/24/2005EP1565989A1 Self-adjusting programmable on-chip clock aligner
08/24/2005CN1659663A Semiconductor memory device with test mode to monitor internal timing control signals at I/O terminals
08/24/2005CN1658327A Semiconductor memory device
08/24/2005CN1658319A Data recording/reproducing system, data recording/reproducing method, program, and recording medium
08/24/2005CN1658171A Faster write operations to nonvolatile memory by manipulation of frequently accessed sectors
08/23/2005US6934904 Data integrity error handling in a redundant storage array
08/23/2005US6934900 Test pattern generator for SRAM and DRAM
08/23/2005US6934899 Variable self-time scheme for write recovery by low speed tester
08/23/2005US6934895 I/O compression circuit for a semiconductor memory device
08/23/2005US6934210 Semiconductor memory circuit
08/23/2005US6934207 Flash array implementation with local and global bit lines
08/23/2005US6934204 Semiconductor device with reduced terminal input capacitance
08/23/2005US6934203 Semiconductor memory device for improving redundancy efficiency
08/23/2005US6934202 Memory circuit with dynamic redundancy
08/23/2005US6934201 Asynchronous, high-bandwidth memory component using calibrated timing elements
08/23/2005US6934200 Yield and speed enhancement of semiconductor integrated circuits using post fabrication transistor mismatch compensation circuitry
08/23/2005US6934179 Semiconductor integrated circuit device and bit line capacitance adjusting method using the device
08/23/2005US6934173 256 Meg dynamic random access memory
08/18/2005WO2005076357A1 Single-poly 2-transistor based fuse element
08/18/2005WO2005076283A1 Nonvolatile semiconductor storing device and block redundancy saving method
08/18/2005WO2005076282A1 Semiconductor storage device
08/18/2005US20050182997 Semiconductor device with memory and method for memory test
08/18/2005US20050182993 Semiconductor integrated circuit device equipped with read sequencer and write sequencer
08/18/2005US20050181554 Semiconductor memory device and method for initializing the same
08/18/2005US20050181546 Methods for fabricating fuse programmable three dimensional integrated circuits
08/18/2005US20050180234 Testing method for permanent electrical removal of an integrated circuit output after packaging
08/18/2005US20050180230 Method and structure for enabling a redundancy allocation during a multi-bank operation
08/18/2005DE60013044T2 Fehlerdetektion und -korrektur Schaltung in eimem Flash-Speicher Error detection and correction circuit in the flash memory eimem
08/17/2005EP1564755A2 Data management apparatus and method of flash memory
08/17/2005EP1564747A1 Semiconductor memory device comprising simultaneous block activation means and method of testing semiconductor memory device
08/17/2005EP1563512A1 2t2c signal margin test mode using resistive element
08/17/2005EP1563511A1 2t2c signal margin test mode using a defined charge and discharge of bl and/bl
08/17/2005EP1563510A1 2t2c signal margin test mode using a defined charge exchange between bl and /bl
08/17/2005CN1656613A Semiconductor memory element and its lifetime operation starting device
08/17/2005CN1656564A Reference voltage generation for memory circuits
08/17/2005CN1655665A Flash memory apparatus having single body type rotary cover
08/17/2005CN1655352A Method and device for storing and presetting microelectronic circuit status
08/17/2005CN1655281A Bias voltage applying circuit and semiconductor memory device
08/17/2005CN1215753C Machine for pick-up of device in processor
08/17/2005CN1215481C Method and circuit for proving reliability of non-volatile internal memory
08/16/2005US6931606 Automatic method and system for instantiating built-in-test (BIST) modules in ASIC memory designs
08/16/2005US6931582 Memory card and memory controller
08/16/2005US6931580 Rapid fail analysis of embedded objects
08/16/2005US6931565 Semiconductor memory
08/16/2005US6931479 Method and apparatus for multi-functional inputs of a memory device
08/16/2005US6930954 Non-volatile semiconductor memory device
08/16/2005US6930938 Semiconductor memory device having test mode
08/16/2005US6930937 Sector synchronized test method and circuit for memory
08/16/2005US6930936 Data compression read mode for memory testing
08/16/2005US6930935 Redundancy circuit and semiconductor device using the same
08/16/2005US6930934 High efficiency redundancy architecture in SRAM compiler
08/16/2005US6930933 Semiconductor memory device which can recover a memory fail
08/16/2005US6930909 Memory device and methods of controlling resistance variation and resistance profile drift
08/16/2005US6930504 Semiconductor integrated circuit device
08/16/2005US6930503 System for testing integrated circuit devices
08/16/2005US6930488 Method and apparatus for accelerated SER testing of circuitry
08/16/2005US6930325 Test structure for improved vertical memory arrays
08/16/2005US6930324 Device architecture and process for improved vertical memory arrays
08/11/2005WO2005072305A2 Efficient modeling of embedded memories in bounded memory checking
08/11/2005WO2005072287A2 Remote bist for high speed test and redundancy calculation
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