Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
09/2005
09/15/2005US20050204235 Automatic method and system for instantiating built-in-test (BIST) modules in ASIC memory designs
09/15/2005US20050204234 Method and apparatus for the memory self-test of embedded memories in semiconductor chips
09/15/2005US20050204232 Technique for combining scan test and memory built-in self test
09/15/2005US20050204231 Testing memories using algorithm selection
09/15/2005US20050204212 Data memory system
09/15/2005US20050204211 Apparatus for determining the access time and/or the minimally allowable cycle time of a memory
09/15/2005US20050201152 Circuit and a method to screen for defects in an addressable line in a non-volatile memory
09/15/2005DE69333606T2 Nichtflüchtiger Halbleiterspeicher mit elektrisch und gemeinsam löschbaren Eigenschaften A non-volatile semiconductor memory having electrically and collectively erasable characteristics
09/15/2005DE19520979B4 Spaltenredundanzvorrichtung für einen Halbleiterspeicher Column redundancy means for a semiconductor memory
09/15/2005DE10353585B4 Unidirektionale Eingangsschaltanordnung, Halbleiterschaltung und Verfahren zur Prüfung einer Laufzeitverzögerung eines Eingangstreibers einer Halbleiterschaltung Unidirectional input circuitry, semiconductor circuit and method for testing a propagation delay of an input driver of a semiconductor circuit
09/15/2005DE10248753B4 Halbleiterbaustein sowie Verfahren zum Funktionstest und zur Konfiguration eines Halbleiterbausteins Semiconductor device and method for functional testing and configuration of a semiconductor device
09/15/2005DE10211932B4 Schaltungsanordnung zum Auslesen, Bewerten und Wiedereinlesen eines Ladungszustandes in eine Speicherzelle Circuitry for reading, evaluating and re-reading a charge state in a memory cell
09/15/2005DE102004008757A1 Parity check switch for continually checking the parity of a memory cell where the number of check stages per data word is equal to the number of bits of the word
09/14/2005EP1573741A2 Two dimensional data eye centering for source synchronous data transfers
09/14/2005CN1669092A Semiconductor memory
09/14/2005CN1669090A Semiconductor memory device and method for initializing the same
09/14/2005CN1667755A Semiconductor device with memory and method for memory test
09/14/2005CN1667753A Methods and circuits for programming of a semiconductor memory cell and memory array
09/13/2005US6944812 Mode entry circuit and method
09/13/2005US6944807 Method and apparatus for achieving higher product yields by using fractional portions of imbedded memory arrays
09/13/2005US6944806 Method and apparatus to data log at-speed March C+ memory BIST
09/13/2005US6944792 Method for verifying user memory validity in operating system
09/13/2005US6944737 Memory modules and methods having a buffer clock that operates at different clock frequencies according to the operating mode
09/13/2005US6944090 Method and circuit for precise timing of signals in an embedded DRAM array
09/13/2005US6944085 Semiconductor memory device with reduced chip area and improved redundancy efficency
09/13/2005US6944074 Semiconductor memory device and method of operating the same
09/13/2005US6944073 Semiconductor integrated circuit device
09/13/2005US6944072 Self-repair method for nonvolatile memory devices with erasing/programming failure, and relative nonvolatile memory device
09/13/2005US6944046 Ferroelectric memory and method of testing the same
09/13/2005US6943764 Driver circuit for an active matrix display device
09/13/2005US6943576 Systems for testing a plurality of circuit devices
09/13/2005US6943575 Method, circuit and system for determining burn-in reliability from wafer level burn-in
09/13/2005US6943541 Apparatus and method for testing circuit modules
09/09/2005WO2005082106A2 Built-in self test method and apparatus for jitter transfer, jitter tolerance, and fifo data buffer
09/09/2005WO2005017959A3 Integrated circuit with test pad structure and method of testing
09/09/2005WO2004042506A3 Methods and apparatus for improved memory access
09/08/2005US20050195677 Method and apparatus for optimizing timing for a multi-drop bus
09/08/2005US20050195666 Memory device including parallel test circuit
09/08/2005US20050195665 Device information writing circuit
09/08/2005US20050195661 Zone boundary adjustment for defects in non-volatile memories
09/08/2005US20050195637 Biasing structure for accessing semiconductor memory cell storage elements
09/08/2005US20050195628 Semiconductor memory device
09/08/2005US20050194614 Integrated semiconductor memory and method for electrically stressing an integrated semiconductor memory
09/08/2005DE19654957B4 Semiconductor DRAM circuit with test mode for personal computer and workstation - has test mode signal setting production circuit outputting respective single test mode sets or both test mode sets depending on signal from condition determination circuit
09/08/2005DE102004008245B3 Integrierter Halbleiterspeicher und Verfahren zum elektrischen Stressen eines integrierten Halbleiterspeichers Integrated semiconductor memory and method for electrically stressing a semiconductor integrated circuit memory
09/08/2005DE102004006288A1 Integrierter Halbleiterspeicher mit redundanten Speicherzellen Integrated semiconductor memory with redundant memory cells
09/08/2005DE10124878B4 Testvorrichtung für Halbleiterbauelemente Test apparatus for semiconductor devices
09/07/2005EP1570490A1 Error recovery for nonvolatile memory
09/07/2005EP1570489A2 Zone boundary adjustment for defects in non-volatile memories
09/07/2005EP1570357A1 Data recovery techniques in storage systems
09/07/2005CN1666110A Electronic circuit with test unit for testing interconnects
09/07/2005CN1664959A Memory device for pre-burning test and method therefor
09/07/2005CN1218378C Producing system of semiconductor storage and method for producing semiconductor storage
09/07/2005CN1218321C Memory device
09/06/2005US6941505 Data processing system and data processing method
09/06/2005US6941495 Low cost built-in self test state machine for general purpose RAM testing
09/06/2005US6941494 Built-in test for multiple memory circuits
09/06/2005US6941420 Log-structure array
09/06/2005US6941413 Nonvolatile memory, its data updating method, and card reader equipped with such nonvolatile memory
09/06/2005US6940781 Semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory
09/06/2005US6940780 Flash array implementation with local and global bit lines
09/06/2005US6940777 Semiconductor device and semiconductor memory device provided with internal current setting adjustment circuit
09/06/2005US6940776 Semiconductor memory device capable of reading data of signature fuse through normal read operation and method of reading data of signature fuse in semiconductor memory device through normal read operation
09/06/2005US6940774 Integrated dynamic memory and operating method
09/06/2005US6940769 Method of driving and testing a semiconductor memory device
09/06/2005US6940767 Semiconductor memory device having a plurality of signal lines for writing and reading data
09/06/2005US6940766 Row-column repair technique for semiconductor memory arrays
09/06/2005US6940765 Repair apparatus and method for semiconductor memory device to be selectively programmed for wafer-level test or post package test
09/06/2005US6940754 Channel erase type nonvolatile semiconductor memory device and electronic card and electronic apparatus using the device
09/01/2005WO2005081261A1 Semiconductor storage device and redundancy control method for semiconductor storage device
09/01/2005WO2005081260A1 Semiconductor storage device and redundancy method for semiconductor storage device
09/01/2005WO2005081257A1 Semiconductor storage device and semiconductor storage device control method
09/01/2005WO2005029504A3 Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance
09/01/2005US20050193294 Wireless no-touch testing of integrated circuits
09/01/2005US20050193293 Semiconductor device capable of performing test at actual operating frequency
09/01/2005US20050193291 Application functionality for a test tool for application programming interfaces
09/01/2005US20050193290 Built-in self test method and apparatus for jitter transfer, jitter tolerance, and FIFO data buffer
09/01/2005US20050193276 Semiconductor IC incorporating a co-debugging function and test system
09/01/2005US20050193274 Method and apparatus for testing a memory device in quasi-operating conditions
09/01/2005US20050193253 A Command Multiplier for Built-In-Self-Test
09/01/2005US20050193241 Method for repairing a semiconductor memory
09/01/2005US20050193163 Integrated circuit buffer device
09/01/2005US20050190629 Method and apparatus for testing circuit units to be tested with different test mode data sets
09/01/2005US20050190618 Semiconductor memory device with reliable fuse circuit
09/01/2005US20050190615 Memory defect detection and self-repair technique
09/01/2005US20050190591 Dynamic semiconductor memory device
09/01/2005DE10336294B4 Temperatursensorschaltung und zugehöriges Auslösetemperatur-Bestimmungsverfahren Temperature sensor circuit and associated operating temperature determination method
08/2005
08/31/2005EP1568046A1 Modular test controller with bist circuit for testing embedded dram circuits
08/31/2005EP1568045A1 Method and system for defining a redundancy window around a particular column in a memory array
08/31/2005EP1568038A1 A method and device to detect the likely onset of thermal relaxation in magnetic data storage devices
08/31/2005CN1662997A Method and apparatus for soft defect detection in a memory
08/31/2005CN1662819A Test method for yielding a known good die
08/31/2005CN1661728A Parity checking circuit for continuous checking of the party of a memory cell
08/31/2005CN1661724A Dynamic semiconductor memory device
08/30/2005US6938193 ECC circuit-containing semiconductor memory device and method of testing the same
08/30/2005US6937536 Antifuse option for row repair
08/30/2005US6937533 Semiconductor integrated circuit provided with semiconductor memory circuit having redundancy function and method for transferring address data
08/30/2005US6937532 Semiconductor memory
08/30/2005US6937531 Memory device and method of storing fail addresses of a memory cell
08/30/2005US6937527 High reliability triple redundant latch with voting logic on each storage node
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