Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
11/2005
11/03/2005US20050243601 Highly compact Eprom and flash EEprom devices
11/03/2005US20050243593 Method for manufacture of semiconductor device
11/03/2005US20050243592 High density data storage device having eraseable bit cells
11/03/2005US20050242829 Circuit module
11/03/2005DE10339787B4 Speichermodul Memory module
11/03/2005DE102004018235A1 Partially defective storage medium e.g. NAND FLASH memory, utilizing method, involves dynamically changing physical position of data blocks, such that frequently used data are accommodated in error free part of medium
11/03/2005DE102004016334A1 Verfahren zum Testen eines integrierten Halbleiterspeichers und integrierter Halbleiterspeicher A method for testing an integrated semiconductor memory device and an integrated semiconductor memory
11/03/2005DE102004015890A1 Memory system for e.g. laptop computer, has set of volatile memory modules and one nonvolatile memory module that stores identifiers, which indicate assignment of volatile memory modules` characteristics in set of volatile memory modules
11/03/2005DE102004015269A1 Integrierte Schaltung Integrated circuit
11/03/2005DE102004001653B3 Verfahren und Vorrichtung zum Testen von zu testenden Schaltungseinheiten mit unterschiedlichen Testmodus-Datensätzen A method and apparatus for testing the circuit under test units with different test mode records
11/02/2005EP1591858A1 Trimming functional parameters in integrated circuits
11/02/2005EP1590810A2 Improved method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array
11/02/2005CN1692452A Semiconductor device and method of controlling the semiconductor device
11/02/2005CN1692448A Method of recovering overerased bits in a memory device
11/02/2005CN1691202A Semiconductor memory device having code bit cell array
11/02/2005CN1691196A Memory device including self-ID information
11/02/2005CN1691139A Method and apparatus for testing tunnel magnetoresistive effect element
11/02/2005CN1690781A Electro-optical device, precharge method thereof, image processing circuit, and electronic apparatus
11/02/2005CN1690724A Circuit and method for testing semiconductor device
11/02/2005CN1225742C Method for quickly identifying element line defect kenel
11/01/2005US6961917 Method for activating fuse units in electronic circuit device
11/01/2005US6961890 Dynamic variable-length error correction code
11/01/2005US6961883 Tester built-in semiconductor integrated circuit device
11/01/2005US6961882 Memory chip and apparatus for testing a memory chip
11/01/2005US6961881 Semiconductor device
11/01/2005US6961880 Recording test information to identify memory cell errors
11/01/2005US6961674 System and method for analysis of cache array test data
11/01/2005US6961275 Device and method for breaking leakage current path of memory device and structure of memory device
11/01/2005US6961273 RAM memory circuit having a plurality of banks and an auxiliary device for testing
10/2005
10/27/2005US20050240851 ROM-based controller monitor in a memory device
10/27/2005US20050240849 Method of testing apparatus having master logic unit and slave logic unit
10/27/2005US20050240842 Circuit and method for testing semiconductor device
10/27/2005US20050240839 Critical area computation of composite fault mechanisms using voronoi diagrams
10/27/2005US20050240838 Semiconductor memory device having code bit cell array
10/27/2005US20050240817 Controlling the generation and selection of addresses to be used in a verification environment
10/27/2005US20050237851 Asynchronous, high-bandwidth memory component using calibrated timing elements
10/27/2005US20050237842 Semiconductor integrated circuit device
10/27/2005US20050237831 Electro-optical device, precharge method thereof, image processing circuit, and electronic apparatus
10/27/2005US20050237830 Redundancy fuse control circuit and semiconductor memory device having the same and redundancy process method
10/27/2005US20050237806 Circuit and method for detecting skew of transistor in semiconductor device
10/27/2005US20050237794 Thin film magnetic memory device capable of conducting stable data read and write operations
10/27/2005US20050237789 Method and apparatus for testing tunnel magnetoresistive effect element
10/27/2005US20050236657 Method of stress-testing an isolation gate in a dynamic random access memory
10/27/2005DE69827949T2 Gerät und verfahren um speicherfehler zu erkennen und zu berichten Device and method to detect memory errors and report
10/27/2005DE19903606B4 Halbleiteranordnung Semiconductor device
10/27/2005DE102005009546A1 Ein Widerstandsänderungssensor A change in resistance sensor
10/27/2005DE102004017284A1 Integrierte Halbleiterschaltung und Verfahren zur Prüfung der integrierten Halbleiterschaltung A semiconductor integrated circuit and method for testing the semiconductor integrated circuit
10/27/2005DE102004015831A1 Integrierte Schaltung Integrated circuit
10/27/2005CA2562030A1 Protecting sub-packets in a wireless network
10/26/2005EP1588380A1 Method for the recognition and/or correction of memory access errors and electronic circuit arrangement for carrying out said method
10/26/2005EP0898284B1 Semiconductor memory having a test circuit
10/26/2005CN1689159A Semiconductor integrated circuit device and method for controlling semiconductor integrated circuit device
10/26/2005CN1224973C Integrated circuit semiconductor device and self-repairing circuit and method for built-in storage
10/25/2005US6959413 Method of handling unreadable blocks during rebuilding of a RAID device
10/25/2005US6959256 Universally accessible fully programmable memory built-in self-test (MBIST) system and method
10/25/2005US6958947 Semiconductor memory device with internal voltage generators for testing a memory array and peripheral circuits
10/25/2005US6958945 Device having a memory array storing each bit in multiple memory cells
10/25/2005US6958942 Circuit calibrating output driving strength of DRAM and method thereof
10/25/2005US6958613 Method for calibrating semiconductor devices using a common calibration reference and a calibration circuit
10/20/2005WO2005098868A1 Test apparatus, phase adjusting method and memory controller
10/20/2005US20050235180 Integrated module having a plurality of separate substrates
10/20/2005US20050234674 Apparatus, system and/or method for converting a serial test to a parallel test
10/20/2005US20050232049 Semiconductor memory device
10/20/2005US20050232040 Test method for a semiconductor memory
10/20/2005US20050232039 Apparatus and method thereof for multiple-time programming using one-time programming device
10/20/2005US20050232038 Semiconductor memory device
10/20/2005US20050232037 Nonvolatile memory apparatus
10/20/2005US20050232036 Semiconductor memory device and method of driving the same
10/20/2005US20050232035 Semiconductor memory device having redundancy cell array shared by a plurality of memory cell arrays
10/20/2005US20050232019 Sequential program-verify method with result buffering
10/20/2005US20050232017 Nonvolatile semiconductor memory device for writing multivalued data
10/20/2005US20050232011 Memory devices with page buffer having dual registers and metod of using the same
10/20/2005US20050231997 Apparatus and methods for ferroelectric ram fatigue testing
10/20/2005US20050231994 Ferroelectric nonvolatile code data output device
10/20/2005US20050231264 Block selection circuit
10/20/2005US20050231251 Apparatus and method for adjusting slew rate in semiconductor memory device
10/20/2005US20050231204 Testing MEM device array
10/20/2005US20050230796 Semiconductor integrated circuit
10/20/2005DE10393735T5 2T2C-Signalspielraumtestmodus durch Verwendung verschiedener Vorladepegel für BL und /BL 2T2C signal margin test mode by using various pre-charge for BL and / BL
10/19/2005EP1587112A2 Buffered memory module with configurable interface width.
10/19/2005EP1586098A1 Multiple trip point fuse latch device and test method of the fuse
10/19/2005EP0921528B1 A memory device using direct access mode test and a method of testing the same
10/19/2005EP0806010A4 Fault tolerant nfs server system and mirroring protocol
10/19/2005EP0726514B1 Methods for using non contiguously reserved storage space for data migration in a redundant hierarchic data storage system
10/19/2005CN1685445A Method and circuitry for identifying weak bits in a MRAM
10/19/2005CN1684201A Test method for a semiconductor memory
10/19/2005CN1684200A Semiconductor storage device
10/19/2005CN1684048A Method and system for secure erasure of information in non-volatile memory in an electronic device
10/19/2005CN1224053C Semiconductor memory used for reducing input cycles of input test mode
10/19/2005CN1223864C IC tester using optical driving type driver and optical output voltage sensor
10/18/2005US6957377 Marking of and searching for initial defective blocks in semiconductor memory
10/18/2005US6957373 Address generator for generating addresses for testing a circuit
10/18/2005US6957372 Repair of address-specific leakage
10/18/2005US6956786 Random access memory with optional inaccessible memory cells
10/18/2005US6956783 Semiconductor memory device including fuse element
10/18/2005US6956778 Semiconductor device having a redundant memory cell and method for recovering the same
10/18/2005US6956777 Semiconductor memory device and control method thereof
10/18/2005US6956772 Programmable fuse and antifuse and method thereof
10/18/2005US6956769 Semiconductor memory device with a flexible redundancy scheme
10/18/2005US6956757 Low cost high density rectifier matrix memory
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