Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
12/2005
12/08/2005US20050270829 Nonvolatile semiconductor memory device having improved redundancy relieving rate
12/08/2005US20050270817 Semiconductor memory device having first and second memory cell arrays and a program method thereof
12/08/2005US20050270058 System for testing integrated circuit devices
12/08/2005DE20023741U1 Digital memory circuit for high bandwidth memory, has multiplexer connected to spare memory and serial output port of shift register, which substitutes fault bit value of serial data stream with spare bit
12/08/2005DE102004059411A1 Flash-Speichervorrichtung und Verfahren zur Steuerung derselben A flash memory device and method for controlling the same
12/08/2005DE102004059410A1 Semiconductor memory device e.g. NAND flash memory device, input/output repair method, involves positioning main and redundancy page buffers in main and redundancy array, respectively
12/07/2005CN1230830C RAM high speed test control circuit and its testing method
12/06/2005US6973613 Error detection/correction code which detects and corrects component failure and which provides single bit error correction subsequent to component failure
12/06/2005US6973605 System and method for assured built in self repair of memories
12/06/2005US6973604 Allocation of sparing resources in a magnetoresistive solid-state storage device
12/06/2005US6973603 Method and apparatus for optimizing timing for a multi-drop bus
12/06/2005US6973404 Method and apparatus for administering inversion property in a memory tester
12/06/2005US6973005 Flash array implementation with local and global bit lines
12/06/2005US6973000 Synchronous semiconductor memory device of fast random cycle system and test method thereof
12/06/2005US6972998 Double data rate memory devices including clock domain alignment circuits and methods of operation thereof
12/06/2005US6972994 Circuit and a method to screen for defects in an addressable line in a non-volatile memory
12/06/2005US6972613 Fuse latch circuit with non-disruptive re-interrogation
12/06/2005US6972612 Semiconductor device with malfunction control circuit and controlling method thereof
12/06/2005US6972587 Built-in self repair for an integrated circuit
12/06/2005US6972585 Semiconductor integrated circuit device and digital measuring instrument
12/06/2005US6972268 Methods and systems for processing a device, methods and systems for modeling same and the device
12/01/2005WO2005114670A1 Pipelined data relocation and improved chip architectures
12/01/2005WO2005078769A3 Manufacturing integrated circuits
12/01/2005US20050268208 Semiconductor memory device and signal processing system
12/01/2005US20050268207 Techniques for operating semiconductor devices
12/01/2005US20050268203 Erasure pointer error correction
12/01/2005US20050268188 Backup method, backup system, disk controller and backup program
12/01/2005US20050268187 Method for deferred data collection in a clock running system
12/01/2005US20050268186 Semiconductor wafer with test circuit and manufacturing method
12/01/2005US20050268185 Method and apparatus for high speed testing of latch based random access memory
12/01/2005US20050268177 Compression of data traces for an integrated circuit with multiple memories
12/01/2005US20050268159 System and method of improving memory yield in frame buffer memory using failing memory location
12/01/2005US20050268034 Diskarray system for suppressing disk fault
12/01/2005US20050265437 Communication channel calibration with nonvolatile parameter store for recovery
12/01/2005US20050265105 Semiconductor device with self refresh test mode
12/01/2005US20050265092 Nonvolatile semiconductor memory device
12/01/2005US20050265091 Semiconductor memory device
12/01/2005US20050265090 Semiconductor storage device
12/01/2005US20050265089 High reliability triple redundant latch with voting logic on each storage node
12/01/2005US20050265073 Non-volatile memory device capable of changing increment of program voltage according to mode of operation
12/01/2005US20050265060 Adjustable timing circuit of an integrated circuit
12/01/2005DE69533764T2 Verfahren zum Gebrauch von Speicherplatten unterschiedlicher Inhalte in einem Einzelvolumen einer hierarchischen Speicherplattenanordnung A method for use of disks of different contents in a single volume a hierarchical disk array
12/01/2005DE102004022328A1 Controlling the temperature of a semiconductor chip, especially a DRAM, by provision of a heating resistance, temperature sensor and temperature regulation element
12/01/2005DE102004022327A1 Integrierter Halbleiterspeicher Integrated semiconductor memory
12/01/2005DE102004022326A1 Verfahren zum Testen eines integrierten Halbleiterspeichers A method for testing an integrated semiconductor memory,
11/2005
11/30/2005EP1600949A1 Diskarray system for suppressing disk fault
11/30/2005EP1595211A4 Compressing test responses using a compactor
11/30/2005EP0980551A4 Moving sectors within a block in a flash memory
11/30/2005CN1703759A Semiconductor storage device, test method therefor, and test circuit therefor
11/30/2005CN1703755A System and method for self-testing and repair of memory modules
11/30/2005CN1703741A Optical disc, and method and apparatus for managing defective areas on write-once type optical disc
11/30/2005CN1702861A Semiconductor device with a plurality of ground planes
11/30/2005CN1702611A Disk array system for suppressing disk fault
11/29/2005US6971055 Method for verifying the accuracy of bit-map memory test programs
11/29/2005US6971053 Method for initiating internal parity operations in a CAM device
11/29/2005US6971052 Semiconductor integrated circuit and method for testing the same
11/29/2005US6970388 Non-volatile semiconductor memory
11/29/2005US6970387 System and method for determining the value of a memory element
11/29/2005US6969623 Semiconductor device and method for manufacturing the same
11/24/2005WO2005112250A2 File download and streaming system
11/24/2005WO2005112040A1 Compression of data traces for an integrated circuit with multiple memories
11/24/2005WO2005066970A3 Robust data duplication and improved update method in a multibit non-volatile memory
11/24/2005US20050262422 Semiconductor memory device for build-in fault diagnosis
11/24/2005US20050262415 Method and apparatus for convolutional interleaving/de-interleaving technique
11/24/2005US20050262405 Apparatus and method for reducing test resources in testing DRAMs
11/24/2005US20050262403 Apparatus and method for single operation read-modify-write in a bit-accessible memory unit memory
11/24/2005US20050262388 Memory controllers with interleaved mirrored memory modes
11/24/2005US20050262292 Memory card
11/24/2005US20050259501 Synchronous global controller for enhanced pipelining
11/24/2005US20050259486 Repair of memory cells
11/24/2005US20050259485 Apparatus and method for testing a memory device
11/24/2005US20050259480 Method and apparatus for providing debug functionality in a buffered memory channel
11/24/2005US20050259478 Memory device including self-ID information
11/24/2005US20050259465 Nonvolatile memory apparatus
11/24/2005US20050259060 Redundancy shift register circuit for driver circuit in active matrix type liquid crystal display device
11/24/2005US20050258456 Memory with integrated programmable controller
11/24/2005DE69034191T2 EEPROM-System mit aus mehreren Chips bestehender Blocklöschung EEPROM system with an existing block of several chips deletion
11/24/2005DE10344879B4 Integrierter Speicher und Verfahren zum Funktionstest des integrierten Speichers Integrated memory and method for functional testing of the integrated memory
11/24/2005DE102005018640A1 Schaltungsmodul Circuit module
11/24/2005DE102005018114A1 Spannungs-/Prozessbewertung bei Halbleitern Voltage / process evaluation in semiconductors
11/24/2005DE102005013900A1 Vorrichtung und Verfahren zum Testen von Halbleitervorrichtungen Apparatus and method for testing semiconductor devices
11/24/2005DE102004021267A1 Verfahren zum Testen eines Speicherbausteins und Prüfanordnung A method for testing a memory device, and setup
11/24/2005DE102004020867A1 Halbleiter-Bauelement-Test-Verfahren, sowie Daten-Zwischenspeicher-Bauelement A semiconductor device testing method, and data latch device
11/24/2005DE102004020866A1 Semiconductor device test method for testing memory module, by using clock signals shifted forward and back by predetermined period compared to normal operation
11/24/2005DE102004020546A1 Elektronische Speichervorrichtung und Verfahren zur Deaktivierung von redundanten Bit- oder Wortleitungen Electronic memory device and method for disabling redundant bit or word lines
11/24/2005DE102004020030A1 Testvorrichtung zum Testen einer integrierten Schaltung Test apparatus for testing an integrated circuit
11/24/2005CA2565989A1 Compression of data traces for an integrated circuit with multiple memories
11/23/2005EP1529293B1 Built-in-self-test of flash memory cells
11/23/2005CN1701391A Method and system for defining a redundancy window around a particular column in a memory array
11/23/2005CN1700357A Semiconductor memory device for build-in fault diagnosis
11/23/2005CN1700356A Semiconductor memory
11/23/2005CN1700353A Memory device having delay locked loop
11/23/2005CN1700346A Method for monitoring an internal control signal of a memory device and apparatus therefor
11/23/2005CN1228787C Nonvolatile internal storage acceleration test method and circuit
11/22/2005US6968545 Method and apparatus for no-latency conditional branching
11/22/2005US6968483 Circuit and method for testing a data memory
11/22/2005US6968482 Memory redundancy with programmable non-volatile control
11/22/2005US6968448 Microsequencer with nested loop counters
11/22/2005US6968427 Built-in self test circuit for testing cache tag array and compare logic
11/22/2005US6967892 Non-volatile semiconductor memory device and memory system using the same
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