Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
11/2005
11/22/2005US6967881 Semiconductor integrated circuit and method of manufacturing of semiconductor integrated circuit
11/22/2005US6967880 Semiconductor memory test device
11/22/2005US6967879 Memory trouble relief circuit
11/22/2005US6967878 Redundancy architecture for repairing semiconductor memories
11/22/2005US6967868 Semiconductor memory device having flexible column redundancy scheme
11/22/2005US6967867 Semiconductor memory device and method for correcting memory cell data
11/17/2005WO2005109446A1 Semiconductor memory device
11/17/2005US20050257121 Method for monitoring an internal control signal of a memory device and apparatus therefor
11/17/2005US20050257120 Pipelined data relocation and improved chip architectures
11/17/2005US20050257112 Method and apparatus for combining de-interleaving with FFT and demapping
11/17/2005US20050257109 Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol
11/17/2005US20050257107 Parallel bit testing device and method
11/17/2005US20050257106 File download and streaming system
11/17/2005US20050257105 Processor array
11/17/2005US20050254325 Semiconductor integrated circuit and method of testing same
11/17/2005US20050254324 Semi-conductor component test procedure, as well as a data buffer component
11/17/2005US20050254323 Method for detecting column fail by controlling sense amplifier of memory device
11/17/2005US20050254322 Flash memory having spare sector with shortened access time
11/17/2005US20050254321 Semiconductor memory
11/17/2005US20050254320 Redundancy circuit for NAND flash memory device
11/17/2005US20050254318 Memory device having delay locked loop
11/17/2005US20050254306 Flash memory device and method for driving the same
11/17/2005US20050254298 Channel erase type nonvolatile semiconductor memory device and electronic card and electronic apparatus using the device
11/17/2005US20050254297 Multi-input/output repair method of nand flash memory device and nand flash memory device thereof
11/17/2005US20050254294 Magnetic random access memory
11/17/2005US20050253644 Trimming functional parameters in integrated circuits
11/17/2005US20050253639 Output driver with pulse to static converter
11/17/2005US20050253615 Parameter measurement of semiconductor device from pin with on die termination circuit
11/17/2005US20050253591 Cell evaluation device
11/16/2005EP1596399A1 Semiconductor memory with refresh and redundancy circuit
11/16/2005EP1595211A2 Compressing test responses using a compactor
11/16/2005CN1697245A Cell evaluation device
11/16/2005CN1697085A Multi-input/output repair method of nand flash memory device and nand flash memory device thereof
11/16/2005CN1697084A Flash memory device and method for driving the same
11/16/2005CN1697078A Semiconductor memory
11/16/2005CN1697077A Semiconductor memory
11/16/2005CN1696906A Method, system and program product for autonomous error recovery for memory devices
11/16/2005CN1227668C Semiconductor memory device and method for selecting multi-word-line in said device
11/15/2005US6966022 System and method for determining integrated circuit logic speed
11/15/2005US6966017 Cache memory self test
11/15/2005US6966016 System and method for erase test of integrated circuit device having non-homogeneously sized sectors
11/15/2005US6966012 Memory column redundancy circuitry and method for implementing the same
11/15/2005US6966011 Data reconstruction method and system wherein timing of data of data reconstruction is controlled in accordance with conditions when a failure occurs
11/15/2005US6965534 Random access memory using precharge timers in test mode
11/15/2005US6965527 Multibank memory on a die
11/15/2005US6965520 Delay system for generating control signals in ferroelectric memory devices
11/10/2005US20050251729 Triple redundant latch design with low delay time
11/10/2005US20050251728 Method for testing a memory chip and test arrangement
11/10/2005US20050251727 Digital data coding apparatus, DVD recording apparatus, and method of using the same
11/10/2005US20050251725 Signal processing methods and systems
11/10/2005US20050251720 Single-ended transmission for direct access test mode within a differential input and output circuit
11/10/2005US20050251718 Method for localization and generation of short critical sequence
11/10/2005US20050251713 Multi-port memory device having serial I/O interface
11/10/2005US20050249018 Multi-port memory device
11/10/2005US20050249016 Method for testing an integrated semiconductor memory
11/10/2005US20050249013 Techniques for storing accurate operating current values
11/10/2005US20050249012 Semiconductor device with self refresh test mode
11/10/2005US20050249002 Integrated semiconductor memory
11/10/2005US20050249001 Testing apparatus and a testing method
11/10/2005US20050249000 Semiconductor memory device for testifying over-driving quantity depending on position
11/10/2005US20050248999 Memory card and memory controller
11/10/2005US20050248998 High speed redundant data sensing method and apparatus
11/10/2005US20050248982 Method and circuit for verifying and eventually substituting defective reference cells of a memory
11/10/2005US20050248976 Dynamic random access memory cell leakage current detector
11/10/2005US20050248387 Boosted voltage generator
11/10/2005US20050248352 Method and system for detecting potential reliability failures of integrated circuit
11/10/2005US20050247930 Shallow trench isolation void detecting method and structure for the same
11/10/2005DE10393845T5 Halbleitertestgerät Semiconductor testing apparatus
11/10/2005DE10393685T5 Hochgeschwindigkeits-Vektorzugriffsverfahren bei einem Musterspeicher für Prüfsysteme High-speed vector access method in a pattern memory for test systems
11/10/2005DE102005011859A1 Ein Entwurf eines dreifach redundanten Latches mit niedriger Verzögerungszeit A design of a triple redundant latches with low delay time
11/10/2005DE102004042252A1 Integrated memory circuit has error recognition unit with compression memory unit for bitline values and error data comparison unit
11/09/2005EP1594140A1 Semiconductor device and method for controlling semiconductor device
11/09/2005EP1419507B1 Method and device for testing semiconductor memory devices
11/09/2005EP0958562B1 Occupancy sensor and method of operating same
11/09/2005CN1695206A Method of and apparatus for detecting an error in writing to persistent memory
11/09/2005CN1695205A Semiconductor memory
11/09/2005CN1694252A Defect tolerant redundancy
11/09/2005CN1694180A Multi-port memory device having serial i/o interface
11/09/2005CN1694178A Multipor memory device
11/08/2005US6964008 Data checksum method and apparatus
11/08/2005US6964000 Semiconductor integrated circuit device having a test circuit of a random access memory
11/08/2005US6963514 Method for testing an integrated semiconductor memory, and integrated semiconductor memory
11/08/2005US6963512 Autotesting method of a memory cell matrix, particularly of the non-volatile type
11/08/2005US6963505 Method circuit and system for determining a reference voltage
11/08/2005US6962827 Semiconductor device capable of shortening test time and suppressing increase in chip area, and method of manufacturing semiconductor integrated circuit device
11/06/2005CA2506641A1 Signal processing methods and systems
11/03/2005WO2005104136A1 Non-volatile semiconductor device and method for automatically correcting non-volatile semiconductor device erase operation failure
11/03/2005WO2004105040A3 Universally accessible fully programmable memory built-in self-test (mbist) system and method
11/03/2005US20050246602 On-chip and at-speed tester for testing and characterization of different types of memories
11/03/2005US20050246598 Voltage/process evaluation in semiconductors
11/03/2005US20050246594 Extender Card for Testing Error-Correction-Code (ECC) Storage Area on Memory Modules
11/03/2005US20050246574 Non-volatile semiconductor memory device
11/03/2005US20050243660 Methods for erasing bit cells in a high density data storage device
11/03/2005US20050243659 Methods for writing and reading highly resolved domains for high density data storage
11/03/2005US20050243638 Memory device tester and method for testing reduced power states
11/03/2005US20050243636 Electronic memory apparatus, and method for deactivating redundant bit lines or word lines
11/03/2005US20050243631 Semiconductor memory circuit
11/03/2005US20050243624 Semiconductor memory device capable of controlling drivability of overdriver
11/03/2005US20050243620 Non-volatile semiconductor memory device
11/03/2005US20050243617 Memory device
1 ... 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 ... 306