Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
12/2005
12/22/2005US20050281113 Data processing system and data processing method
12/22/2005US20050281103 Semiconductor integrated circuit and operational amplifier
12/22/2005US20050281102 Semiconductor structure processing using multiple laterally spaced laser beam spots with joint velocity profiling
12/22/2005US20050281101 Semiconductor structure processing using multiple laterally spaced laser beam spots with on-axis offset
12/22/2005US20050281088 External storage device
12/22/2005US20050281070 Ferroelectric memory device, electronic apparatus
12/22/2005US20050280479 Circuits and methods of temperature compensation for refresh oscillator
12/22/2005US20050280452 Interpolator testing system
12/22/2005US20050280165 Multi-chip packaged integrated circuit device for transmitting signals from one chip to another chip
12/22/2005US20050280072 Test mode decoder in a flash memory
12/22/2005US20050280036 Semiconductor product having a first and at least one further semiconductor circuit and method
12/22/2005DE102005026663A1 Nichtflüchtiges Speicherbauelement mit ISPP Non-volatile memory device with ISPP
12/22/2005DE102004025893A1 Testvorrichtung mit Speicherdatenumsetzer für redundante Bit- und Wortleitungen Test device with memory data converter for redundant bit and word lines
12/21/2005EP1607984A1 Method for managing bad memory blocks in a nonvolatile memory device, and nonvolatile memory device implementing the management method
12/21/2005EP1607867A1 Data management method for slash memory medium
12/21/2005EP1606824A1 Test for weak sram cells
12/21/2005CN1710663A Ferroelectric memory device, electronic apparatus
12/20/2005US6978411 Memory test system for peak power reduction
12/20/2005US6978408 Generating array bit-fail maps without a tester using on-chip trace arrays
12/20/2005US6978407 Method and architecture for detecting random and systematic transistor degradation for transistor reliability evaluation in high-density memory
12/20/2005US6978406 System and method for testing memory arrays
12/20/2005US6978405 Memory device with comparison units to check functionality of addressed memory cells
12/20/2005US6978402 Semiconductor memory
12/20/2005US6978352 Memory controller emulator for controlling memory devices in a memory system
12/20/2005US6978342 Moving sectors within a block of information in a flash memory mass storage architecture
12/20/2005US6977862 Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuit
12/20/2005US6977861 Nonvolatile semiconductor memory device
12/20/2005US6977858 Semiconductor device
12/20/2005US6977855 Apparatus and method for dynamically repairing a semiconductor memory
12/20/2005US6977854 Flash array implementation with local and global bit lines
12/20/2005US6977853 Flash array implementation with local and global bit lines
12/20/2005US6977852 ROM-based controller monitor in a memory device
12/20/2005US6977851 Semiconductor memory device
12/20/2005US6977512 Method and apparatus for characterizing shared contacts in high-density SRAM cell design
12/20/2005US6977410 Test mode decoder in a flash memory
12/15/2005WO2005077024A3 Methods and apparatus for data analysis
12/15/2005US20050278612 Storage device parity computation
12/15/2005US20050278600 Memory size allocation device and method applying in interleaving
12/15/2005US20050278599 Testing device
12/15/2005US20050278597 Methods and apparatus for data analysis
12/15/2005US20050278596 Semiconductor integrated circuit device
12/15/2005US20050278595 Built-in self test circuit and test method for storage device
12/15/2005US20050278592 Semiconductor memory
12/15/2005US20050278591 System and method for testing a data storage device without revealing memory content
12/15/2005US20050278481 Contiguous block addressing scheme
12/15/2005US20050276369 Shift register and electronic device using the same
12/15/2005US20050276146 Semiconductor memory device
12/15/2005US20050276144 Temperature detector providing multiple detected temperature points using single branch and method of detecting shifted temperature
12/15/2005US20050276134 Memory device
12/15/2005US20050276131 Semiconductor memory device and burn-in test method therefor
12/15/2005US20050276130 Contiguous block addressing scheme
12/15/2005US20050276129 Integrated circuit memory with fast page mode verify
12/15/2005US20050276128 Redundancy circuits and memory devices having a twist bitline scheme and methods of repairing defective cells in the same
12/15/2005US20050276122 Efficient recovery of failed memory cell
12/15/2005US20050276121 Contiguous block addressing scheme
12/15/2005US20050276113 Semiconductor integrated circuit device incorporating a data memory testing circuit
12/15/2005US20050276087 Large scale integrated circuit and at speed test method thereof
12/15/2005DE102005004164A1 Speichervorrichtungs-Steuereinheit zum Analysieren von Datenträgerinhalts-Information und Steuerverfahren The storage device control unit for analyzing data carriers content information and control method
12/15/2005DE102004060350A1 Redundancy circuit for NAND flash memory device, applies external data to main page buffer unit or redundancy page buffer unit according to redundancy control signal from contact addressable memory cell
12/15/2005DE102004024668A1 Verfahren zum Testen von elektronischen Schaltungseinheiten und Testvorrichtung A method for testing electronic circuit units and the test device
12/14/2005EP1604372A1 Memory built-in self-test (bist) architecture having distributed command interpretation and generalized command protocol
12/14/2005CN1708905A Self-adjusting programmable on-chip clock aligner
12/14/2005CN1708808A Enabling memory redundancy during testing
12/14/2005CN1707696A Memory device
12/14/2005CN1707689A Magnetic random access memory
12/14/2005CN1707454A Hub, memory module, memory system and methods for reading and writing to the same
12/14/2005CN1707446A Nonvolatile memory apparatus
12/14/2005CN1231918C Semiconductor storage device, its testing method, and test circuit
12/14/2005CN1231917C Thin film magnet memory capable of stably reading- out data and writing- in data
12/14/2005CN1231842C Flash storage device with all-in-one rotation casing
12/13/2005US6976204 Circuit and method for correcting erroneous data in memory for pipelined reads
12/13/2005US6976200 Semiconductor integrated circuit having bonding optional function
12/13/2005US6976198 Self-repairing integrated circuit and method of operating the same
12/13/2005US6976197 Apparatus and method for error logging on a memory module
12/13/2005US6976195 Method and apparatus for testing a memory device with compressed data using a single output
12/13/2005US6976194 Memory/Transmission medium failure handling controller and method
12/13/2005US6975559 Device and method for reading non-volatile memories having at least one pseudo-parallel communication interface
12/13/2005US6975558 Integrated circuit device
12/13/2005US6975548 Memory device having redundant memory cell
12/13/2005US6975144 System, method and apparatus for improving sense amplifier performance characteristics using process feedback
12/08/2005WO2005117027A1 Repair of memory cells
12/08/2005WO2005116838A1 Configurable width buffered module having a bypass circuit
12/08/2005WO2005041107A3 A method circuit and system for determining a reference voltage
12/08/2005US20050273680 Semiconductor device having buffer layer pattern and method of forming same
12/08/2005US20050273679 Semi-conductor component test procedure, in particular for a system with several modules, each comprising a data buffer component, as well as a test module to be used in a corresponding procedure
12/08/2005US20050273678 Test apparatus for testing an integrated circuit
12/08/2005US20050273677 Circuit and method for storing a signal using a latch shared between operational and diagnostic paths
12/08/2005US20050273670 Multi-port memory device
12/08/2005US20050271179 Multi-strobe generation apparatus, test apparatus and adjustment method
12/08/2005US20050270890 Circuit and method for detecting frequency of clock signal and latency signal generation circuit of semiconductor memory device with the circuit
12/08/2005US20050270878 Nonvolatile semiconductor memory and method of operating the same
12/08/2005US20050270869 Transistor
12/08/2005US20050270868 Semiconductor memory device and method for adjusting internal voltage thereof
12/08/2005US20050270866 Enabling memory redundancy during testing
12/08/2005US20050270865 Test apparatus with memory data converter for redundant bit and word lines
12/08/2005US20050270863 Redundancy repair circuit and a redundancy repair method therefor
12/08/2005US20050270862 Apparatus and method for semiconductor device repair with reduced number of programmable elements
12/08/2005US20050270859 Test method and test circuit for electronic device
12/08/2005US20050270848 Non-volatile memory device capable of changing increment of program voltage according to mode of operation
12/08/2005US20050270842 Nonvolatile memory
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