Patents
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
02/2006
02/16/2006DE19781328B4 Speichertestgerät Memory tester
02/16/2006DE19639972B4 Hochgeschwindigkeitstestschaltkreis für eine Halbleiterspeichervorrichtung High-speed test circuit for a semiconductor memory device
02/16/2006DE10335978B4 Hub-Baustein zum Anschließen von einem oder mehreren Speicherbausteinen Hub module for connecting one or more storage devices
02/16/2006DE102004035549A1 Process for replacing a defective memory chip uses substitute module to replace both defective and surrounding cells
02/16/2006DE10026276B4 Halbleiterschaltungsanordnung Semiconductor circuitry
02/15/2006EP1626413A1 A row decoder for nand memoiries
02/15/2006EP1625573A1 Method of error correction coding, and apparatus for and method of recording data using the coding method
02/15/2006CN1734675A Integrated circuit memory with fast page mode verify
02/15/2006CN1242416C Protection circuit
02/15/2006CN1242415C Semiconductor memory device power control method and semiconductor memory device
02/15/2006CN1242329C Automatic insert method for semiconductor integrated circuit and simplified circuit test
02/14/2006US7000171 Recorded medium reproducing device and method, data output controlling method, data outputting method, error detecting method, and data outputting reproducing method
02/14/2006US7000160 Semiconductor integrated circuit and a method of testing the same
02/14/2006US7000159 System and method for testing memory
02/14/2006US7000156 Devices for storing and accumulating defect information, semiconductor device and device for testing the same
02/14/2006US7000155 Redundancy register architecture for soft-error tolerance and methods of making the same
02/14/2006US7000062 System and method featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices
02/14/2006US6999887 Memory cell signal window testing apparatus
02/14/2006US6999366 Magnetic memory including a sense result category between logic states
02/14/2006US6999363 Non-volatile memory with test rows for disturb detection
02/14/2006US6999362 Method of stress-testing an isolation gate in a dynamic random access memory
02/14/2006US6999361 Method and apparatus for data compression in memory devices
02/14/2006US6999360 Shift redundancy circuit, method for controlling shift redundancy circuit, and semiconductor memory device
02/14/2006US6999359 Method for screening failure of memory cell transistor
02/14/2006US6999358 Semiconductor memory device
02/14/2006US6999357 Memory circuit with redundant memory cell array allowing simplified shipment tests and reduced power consumptions
02/14/2006US6999356 Semiconductor device capable of readjusting a reference potential during the reliabilty test
02/14/2006US6999353 Semiconductor memory device including page latch circuit
02/14/2006US6999349 Semiconductor nonvolatile storage device
02/14/2006US6999347 Non-volatile semiconductor memory device with expected value comparison capability
02/14/2006US6999341 Thin-film magnetic memory device with memory cells having magnetic tunnel junction
02/14/2006US6999340 Semiconductor memory device including reference memory cell and control method
02/14/2006US6999339 Integrated circuit including sensor to sense environmental data, method of compensating an MRAM integrated circuit for the effects of an external magnetic field, MRAM integrated circuit, and method of testing
02/14/2006US6999336 Ferroelectric memory
02/14/2006US6999334 System and method for determining the logic state of a memory cell in a magnetic tunnel junction memory device
02/14/2006US6999333 Method and apparatus for assessing one-time programmable cells
02/14/2006US6998892 Method and apparatus for accommodating delay variations among multiple signals
02/14/2006US6998868 Test key for bridge and continuity testing
02/09/2006WO2006013529A1 Data storage and replay apparatus
02/09/2006WO2005114670B1 Pipelined data relocation and improved chip architectures
02/09/2006US20060031739 Converting circuitforpreventing wrong errorcorrection codes from occurring due to an error correction rule duringdata reading operation
02/09/2006US20060031726 Programmable multi-mode built-in self-test and self-repair structure for embedded memory arrays
02/09/2006US20060031725 Algorithm pattern generator for testing a memory device and memory tester using the same
02/09/2006US20060028900 Memory device employing open bit line architecture for providing identical data topology on repaired memory cell block and method thereof
02/09/2006US20060028885 Synchronous semiconductor memory device of fast random cycle system and test method thereof
02/09/2006US20060028884 Nonvolatile semiconductor memory device
02/09/2006US20060028883 Information storage device, information storage method, and information storage program
02/09/2006US20060028853 Semiconductor device
02/09/2006US20060028655 Methods and systems for precisely relatively positioning a waist of a pulsed laser beam and method and system for controlling energy delivered to a target structure
02/09/2006DE19924153B4 Schaltungsanordnung zur Reparatur eines Halbleiterspeichers Circuit arrangement for repairing a semiconductor memory
02/08/2006EP1624465A1 Programmable multi-mode built-in self-test and self-repair structure for embedded memory arrays
02/08/2006EP1624464A1 Built-in self diagnosis device for a random access memory and method of diagnosing a random access memory
02/08/2006EP1624463A1 A Programmable memory device with an improved redundancy structure
02/08/2006EP1624461A2 Writable tracking cells
02/08/2006EP1624458A1 Adaptive algorithm for MRAM manufacturing
02/08/2006CN1732537A Method of addressing individual memory devices on a memory module
02/08/2006CN1731363A Method and apparatus for a modified parity check
02/08/2006CN1241206C Memory equipment having page buffer with double-register and using method thereof
02/08/2006CN1241205C Address generating circuit
02/07/2006US6996766 Error detection/correction code which detects and corrects a first failing component and optionally a second failing component
02/07/2006US6996760 ASIC BIST employing stored indications of completion
02/07/2006US6996755 Squence control circuit
02/07/2006US6996754 Integrated circuit device having an internal state monitoring function
02/07/2006US6996753 Wafer burn-in test mode circuit
02/07/2006US6996752 System, method, and computer program product within a data processing system for converting a spare storage device to a defined storage device in a logical volume
02/07/2006US6996749 Method and apparatus for providing debug functionality in a buffered memory channel
02/07/2006US6996020 Semiconductor memory device
02/07/2006US6996017 Redundant memory structure using bad bit pointers
02/07/2006US6996014 Memory devices with page buffer having dual registers and method of using the same
02/02/2006US20060026489 Nonvolatile memory and nonvolatile memory apparatus
02/02/2006US20060026482 Test apparatus
02/02/2006US20060023526 Semiconductor memory test apparatus
02/02/2006US20060023525 Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
02/02/2006US20060023524 Nonvolatile semiconductor memory and method for setting replacement information in nonvolatile semiconductor memory
02/02/2006US20060023514 Semiconductor nonvolatile storage device
02/02/2006DE69634778T2 Vorrichtung zum parallelen prüfen von halbleiterschaltkreisen Apparatus for parallel check of semiconductor switching circuits
02/02/2006DE19752212B4 Störereigniszählvorrichtung Störereigniszählvorrichtung
02/02/2006DE19730347B4 Statische Halbleitervorrichtung, die eine variable Stromversorgungsspannung, die an eine Speicherzelle angelegt wird, abhängig von dem Status im Gebrauch aufweist, und Verfahren zum Testen derselben Static semiconductor device, which, depending has a variable power supply voltage, which is applied to a memory cell from the state in use, and methods of testing same
02/02/2006DE19612407B4 Halbleiterspeichereinrichtung A semiconductor memory device
02/02/2006DE10356851B4 Schieberegister zum sicheren Bereitstellen eines Konfigurationsbits Shift register for providing a safe configuration bits
02/01/2006EP1622167A2 Cache memory and processor and their production methods
02/01/2006EP1620857A1 Enabling memory redundancy during testing
02/01/2006CN1729400A Semiconductor test instrument
02/01/2006CN1728284A Method for seanning flash memory chip in flash memory disk
02/01/2006CN1728283A Apparatus and method for testing semiconductor memory device
02/01/2006CN1240076C Semiconductor storage device
01/2006
01/31/2006USRE38956 Data compression circuit and method for testing memory devices
01/31/2006US6993701 Row-diagonal parity technique for enabling efficient recovery from double failures in a storage array
01/31/2006US6993696 Semiconductor memory device with built-in self test circuit operating at high rate
01/31/2006US6993692 Method, system and apparatus for aggregating failures across multiple memories and applying a common defect repair solution to all of the multiple memories
01/31/2006US6993691 Series connected TC unit type ferroelectric RAM and test method thereof
01/31/2006US6993690 Memory unit having memory status indicator
01/31/2006US6993688 Data sector error tracking and correction mechanism
01/31/2006US6992949 Method and circuit for controlling generation of column selection line signal
01/31/2006US6992939 Method and apparatus for identifying short circuits in an integrated circuit device
01/31/2006US6992938 Methods and apparatuses for test circuitry for a dual-polarity non-volatile memory cell
01/31/2006US6992937 Column redundancy for digital multilevel nonvolatile memory
01/31/2006US6992924 Magnetic memory and method for optimizing write current in a magnetic memory
01/31/2006US6992911 Semiconductor memory device
01/31/2006US6992534 Circuits and methods of temperature compensation for refresh oscillator