| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 01/31/2006 | US6992498 Test apparatus for testing integrated modules and method for operating a test apparatus |
| 01/31/2006 | US6991970 Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of semiconductor device |
| 01/26/2006 | US20060020747 Moving sectors within a block of information in a flash memory mass storage architecture |
| 01/26/2006 | US20060018167 Flash memory device capable of reducing test time and test method thereof |
| 01/26/2006 | US20060018166 Method and managing bad memory blocks in a nonvolatile memory device, and nonvolatile-memory device implementing the management method |
| 01/26/2006 | US20060018159 Programmable NAND memory |
| 01/26/2006 | US20060018148 Method and device to detect the likely onset of thermal relaxation in magnetic data storage devices |
| 01/26/2006 | DE102004047719A1 Device for testing circuit unit with increased clock frequency has device for switching connection device between normal and frequency doubling modes with clock signal and frequency doubled clock signal fed to circuit unit respectively |
| 01/25/2006 | EP1619582A2 ECC circuit-containing semiconductor memory device and method of testing the same |
| 01/25/2006 | EP1123556B1 Fuse circuit having zero power draw for partially blown condition |
| 01/25/2006 | CN1726560A Two dimensional data eye centering for source synchronous data transfers |
| 01/25/2006 | CN1725383A Soft ware and hardware combined monitoring and correcting method |
| 01/25/2006 | CN1725382A Detection method of flash storage |
| 01/25/2006 | CN1725380A On-chip ee-prom programming waveform generation |
| 01/25/2006 | CN1725371A Semiconductor memory device |
| 01/25/2006 | CN1238893C Programmed method and device |
| 01/25/2006 | CN1238858C Method for testing memory apparatus |
| 01/24/2006 | US6990640 DIMM and method for producing a DIMM |
| 01/24/2006 | US6990623 Method for error detection/correction of multilevel cell memory and multilevel cell memory having error detection/correction function |
| 01/24/2006 | US6990622 Method for error correction decoding in an MRAM device (historical erasures) |
| 01/24/2006 | US6990617 Semiconductor memory device and test method of the same |
| 01/24/2006 | US6990614 Data storage apparatus and data measuring apparatus |
| 01/24/2006 | US6990613 Test apparatus |
| 01/24/2006 | US6990030 Magnetic memory having a calibration system |
| 01/24/2006 | US6990027 Semiconductor memory device having access time control circuit |
| 01/24/2006 | US6990005 Semiconductor device |
| 01/24/2006 | US6989707 Semiconductor circuit and initialization method |
| 01/24/2006 | US6989551 Test structure for determining a minimum tunnel opening size in a non-volatile memory |
| 01/24/2006 | US6989508 High-speed, precision, laser-based method and system for processing material of one or more targets within a field |
| 01/19/2006 | US20060015802 Layered decoding approach for low density parity check (LDPC) codes |
| 01/19/2006 | US20060015793 Method of combining multilevel memory cells for an error correction scheme |
| 01/19/2006 | US20060015788 Semiconductor device |
| 01/19/2006 | US20060015784 System and method for write-enable bypass testing in an electronic circuit |
| 01/19/2006 | US20060013049 Semiconductor memory device with small number of repair signal transmission lines |
| 01/19/2006 | US20060013048 Memory systems including defective block management and related methods |
| 01/19/2006 | US20060013030 Refresh-free dynamic semiconductor memory device |
| 01/19/2006 | US20060013029 Low cost high density rectifier matrix memory |
| 01/19/2006 | DE19640437B4 Spaltenredundanzschaltkreis Column redundancy circuit |
| 01/19/2006 | DE10323413B4 Prüfverfahren, Prüfsockel und Prüfanordnung für Hochgeschwindigkeits- Halbleiterspeichereinrichtungen Test methods, test socket, and setup for high-speed semiconductor memory devices |
| 01/19/2006 | DE102004030602A1 Paralleler Datenbus Parallel data bus |
| 01/19/2006 | DE102004027854A1 Testvorrichtung und Verfahren zum Testen von zu testenden Schaltungseinheiten A test device and method for testing the circuit under test units |
| 01/18/2006 | EP1617438A1 Redundancy based NAND flash memory |
| 01/18/2006 | CN1723449A Memory device with built-in test function and method for controlling the same |
| 01/18/2006 | CN1722307A Memory test circuit and method |
| 01/18/2006 | CN1722306A Method of testing a memory module and hub of the memory module |
| 01/18/2006 | CN1722299A Ferroelectric memory device |
| 01/18/2006 | CN1722100A Internal memory test system and method |
| 01/18/2006 | CN1237545C Variable domain redundancy replacement configuration for memory device |
| 01/17/2006 | US6988237 Error-correction memory architecture for testing production errors |
| 01/17/2006 | US6988232 Method and apparatus for optimized parallel testing and access of electronic circuits |
| 01/17/2006 | US6988046 Test method of memory IC function on device board with dynamic competing cycle |
| 01/17/2006 | US6987703 Nonvolatile semiconductor storage device and write time determining method therefor |
| 01/17/2006 | US6987702 Method and apparatus for data compression in memory devices |
| 01/12/2006 | WO2006004421A1 Operating temperature optimization in a ferroelectric or electret memory |
| 01/12/2006 | US20060010359 Method for testing electronic circuit units and test apparatus |
| 01/12/2006 | US20060010343 Data reconstruction method and system wherein timing of data of data reconstruction is controlled in accordance with conditions when a failure occurs |
| 01/12/2006 | US20060010335 Method and apparatus for reconfigurable memory |
| 01/12/2006 | US20060007764 Semiconductor fabrication that includes surface tension control |
| 01/12/2006 | US20060007763 Memory row/column replacement in an integrated circuit |
| 01/12/2006 | US20060007762 Memory array decoder |
| 01/12/2006 | US20060007761 Memory module with termination component |
| 01/12/2006 | US20060007739 Semiconductor device and test method thereof |
| 01/12/2006 | US20060007722 Operating temperature optimization in a ferroelectric or electret memory |
| 01/12/2006 | US20060006419 Method of testing a memory module and hub of the memory module |
| 01/12/2006 | DE69534057T2 Verfahren zur Vermeidung der Über-Zuteilung virtueller Kapazität in einem redundanten hierarchischen Datenspeichersystem Method for avoiding the over-allocation of virtual capacity in a redundant hierarchic data storage system |
| 01/12/2006 | DE10052292B4 Halbleiterspeicher mit Datenspeicher und elektrisch lösch- und programmierbarer Array-Logik A semiconductor memory with data memory and electrically erasable and programmable array logic |
| 01/12/2006 | DE10024640B4 Verzögerungssignal-Erzeugungsvorrichtung und Halbleiterprüfvorrichtung Delay signal generating apparatus and semiconductor testing |
| 01/11/2006 | EP1614120A1 Magnetic memory cell including a fuse element for disconnecting the defective magnetic element |
| 01/11/2006 | EP1543526A4 Method of recovering overerased bits in a memory device |
| 01/11/2006 | EP0936611B1 Information recording method and apparatus |
| 01/11/2006 | CN1720590A Automated wear leveling in non-volatile storage systems |
| 01/11/2006 | CN1236453C Semiconductor memory |
| 01/10/2006 | US6986114 Feedback cycle detection across non-scan memory elements |
| 01/10/2006 | US6986095 Error correction device |
| 01/10/2006 | US6986088 Method and apparatus for reducing the current consumption of an electronic circuit |
| 01/10/2006 | US6986084 Apparatus and method for reducing test resources in testing DRAMS |
| 01/10/2006 | US6986083 Method and/or apparatus for SCSI target verification |
| 01/10/2006 | US6986082 Testing system for semiconductor memory device |
| 01/10/2006 | US6985401 Memory device having delay locked loop |
| 01/10/2006 | US6985400 On-die detection of the system operation frequency in a DRAM to adjust DRAM operations |
| 01/10/2006 | US6985396 Semiconductor integrated circuit |
| 01/10/2006 | US6985395 Semiconductor memory device and method of testing the device |
| 01/10/2006 | US6985393 Device for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines |
| 01/10/2006 | US6985392 Byte aligned redundancy for memory array |
| 01/10/2006 | US6985391 High speed redundant data sensing method and apparatus |
| 01/10/2006 | US6985390 Integrated memory circuit having a redundancy circuit and a method for replacing a memory area |
| 01/10/2006 | US6984534 Method and device for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal |
| 01/05/2006 | WO2006002334A2 Intelligent probe chips/heads |
| 01/05/2006 | US20060005108 Intelligent error checking method and mechanism |
| 01/05/2006 | US20060005107 Error correction in ROM embedded DRAM |
| 01/05/2006 | US20060005105 Decoder and decoding method for decoding low-density parity-check codes with parity check matrix |
| 01/05/2006 | US20060005098 Interface workbench for high volume data buffering and connectivity |
| 01/05/2006 | US20060005096 Scan stream sequencing for testing integrated circuits |
| 01/05/2006 | US20060005088 System and method for testing artificial memory |
| 01/05/2006 | US20060002226 Semiconductor memory device |
| 01/05/2006 | US20060002212 Semiconductor device |
| 01/05/2006 | US20060002209 Mode entry circuit and method |
| 01/05/2006 | US20060002208 Housing for a semiconductor device and semiconductor device testing system for testing the contacting for semiconductor devices positioned one above the other |
| 01/05/2006 | US20060002207 ROM test method and ROM test circuit |
| 01/05/2006 | US20060002206 Data path having grounded precharge operation and test compression capability |