| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 01/05/2006 | US20060002205 Semiconductor device having relief circuit for relieving defective portion |
| 01/05/2006 | US20060002204 Redundancy program circuit and methods thereof |
| 01/05/2006 | US20060002203 Input device having activating means |
| 01/05/2006 | US20060002202 Mask ROM devices of semiconductor devices and method of forming the same |
| 01/05/2006 | US20060002193 System and method for determining the value of a memory element |
| 01/05/2006 | US20060002187 Programmable fuse and antifuse and method therefor |
| 01/05/2006 | US20060001441 Method for universally testing semiconductor devices with different pin arrangement |
| 01/05/2006 | DE69533575T2 Verfahren der und System zur Speicherplatzreservierung für Datenmigration in einem hierarchischen Datenspeicherungssystem durch dynamische Berechnung maximalen Speicherplatzes für Spiegelredundanz Method of and system for space allocation for data migration in a hierarchical data storage system by dynamically calculating maximum storage space for mirror redundancy |
| 01/05/2006 | DE102005015828A1 Hub for memory module e.g. fully buffered dual-in-line memory module, has controller which ignores memory identification information in response to southbound packet from memory controller when writing packet data during test mode |
| 01/04/2006 | EP1612807A2 Random access memory array with parity bit architecture |
| 01/04/2006 | EP0907185B1 Floating bitline test mode with digitally controllable bitline equalizers |
| 01/04/2006 | CN1717750A Modular test controller with bist circuit for testing embedded dram circuits |
| 01/04/2006 | CN1717749A Self-repair of memory arrays using preallocated redundancy (PAR) architecture |
| 01/04/2006 | CN1717744A A method and device to detect the likely onset of thermal relaxation in magnetic data storage devices |
| 01/04/2006 | CN1716763A Semiconductor integrated circuit and operational amplifier circuit |
| 01/04/2006 | CN1716450A Method for managing access to flash storage data |
| 01/04/2006 | CN1716449A Apparatus and method for detecting multiple hits in CAM arrays |
| 01/04/2006 | CN1235289C Fuse circuit used for semiconductor integrated circuit |
| 01/04/2006 | CN1235230C Method for detecting memory by utilizing continuous data change |
| 01/04/2006 | CN1235140C System and method for developing custom-made identification of integrated testing and network peripheral equipment |
| 01/03/2006 | US6983441 Embedding a JTAG host controller into an FPGA design |
| 01/03/2006 | US6983413 Data processing method using error-correcting code and an apparatus using the same method |
| 01/03/2006 | US6983404 Method and apparatus for checking the resistance of programmable elements |
| 01/03/2006 | US6982920 Flash array implementation with local and global bit lines |
| 01/03/2006 | US6982912 Semiconductor memory device |
| 01/03/2006 | US6982911 Memory device with common row interface |
| 01/03/2006 | US6982904 Non-volatile semiconductor memory device and electric device with the same |
| 01/03/2006 | US6982900 Semiconductor integrated circuit device |
| 12/29/2005 | WO2004109751A3 Fault tolerant data storage circuit |
| 12/29/2005 | US20050289443 Method and apparatus for additive trellis encoding |
| 12/29/2005 | US20050289441 Semiconductor device improving error correction processing rate |
| 12/29/2005 | US20050289440 System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem |
| 12/29/2005 | US20050289439 System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem |
| 12/29/2005 | US20050289436 Data integrity checking |
| 12/29/2005 | US20050289423 Built-in self test systems and methods for multiple memories |
| 12/29/2005 | US20050289417 Scan enabled storage device |
| 12/29/2005 | US20050289415 Intelligent probe chips/heads |
| 12/29/2005 | US20050289413 Integrated semiconductor memory |
| 12/29/2005 | US20050289412 Parallel bit test circuit in semiconductor memory device and associated method |
| 12/29/2005 | US20050289410 Internal signal test device and method thereof |
| 12/29/2005 | US20050289409 Parallel data bus |
| 12/29/2005 | US20050289407 Associative memory capable of searching for data while keeping high data reliability |
| 12/29/2005 | US20050289389 Storage device employing a flash memory |
| 12/29/2005 | US20050289287 Method and apparatus for interfacing between test system and embedded memory on test mode setting operation |
| 12/29/2005 | US20050286506 System and method for an asynchronous data buffer having buffer write and read pointers |
| 12/29/2005 | US20050286338 Adjustable timing circuit of an integrated circuit |
| 12/29/2005 | US20050286337 Handling defective memory blocks of NAND memory devices |
| 12/29/2005 | US20050286336 Flash EEprom system |
| 12/29/2005 | US20050286335 Memory device for reducing leakage current |
| 12/29/2005 | US20050286326 Method and apparatus for data compression in memory devices |
| 12/29/2005 | US20050286325 Method and apparatus for data compression in memory devices |
| 12/29/2005 | US20050286324 Semiconductor memory device |
| 12/29/2005 | US20050286323 Semiconductor memory device and circuit layout of dummy cell |
| 12/29/2005 | US20050286289 Ferroelectric memory device |
| 12/29/2005 | US20050285626 Circuits and methods of temperature compensation for refresh oscillator |
| 12/29/2005 | US20050285614 Wafer probecard interface |
| 12/29/2005 | DE69732637T2 Selbsttest und Korrektur von Ladungsverlustfehlern in einem Sektorenlöschbaren und-programmierbaren Flashspeicher Self-test and correction of errors in a loss of charge and Sektorenlöschbaren-programmable Flash memory |
| 12/29/2005 | DE102005026636A1 Non-volatile memory e.g. flash memory, device, has multiplexer circuit with program controller generating step control signals such that increment of voltage is varied according to mode of operation |
| 12/29/2005 | DE102004030053B3 Halbleiterspeichervorrichtung A semiconductor memory device |
| 12/29/2005 | DE102004027275A1 Integrierter Halbleiterspeicher Integrated semiconductor memory |
| 12/29/2005 | DE102004027273A1 Halbleiterbaustein mit einer ersten und mindestens einer weiteren Halbleiterschaltung und Verfahren A semiconductor device having a first and at least a further semiconductor circuit and method |
| 12/29/2005 | DE102004026800A1 Verfahren zum Verändern einer Tiefe einer Interleaver-Vorrichtung oder Deinterleaver-Vorrichtung sowie entsprechende Interleaver-Vorrichtung und Deinterleaver-Vorrichtung A method for changing a depth of interleaver device or deinterleaver device and corresponding interleaver and deinterleaver device-device |
| 12/29/2005 | DE102004026248A1 Halbleiter-Bauelement-Test-Verfahren, insbesondere für ein System mit mehreren jeweils ein Daten-Zwischenspeicher-Bauelement aufweisenden Modulen, sowie Test-Modul zur Verwendung bei einem derartigen Verfahren A semiconductor device testing method, in particular for a system having a plurality each have a data latch device having modules, as well as test module for use in such a method |
| 12/29/2005 | DE102004026128A1 Integrierter Halbleiterspeicher mit mindestens einer Wortleitung und mit einer Vielzahl von Speicherzellen Integrated semiconductor memory having at least one word line and a plurality of memory cells |
| 12/28/2005 | EP1610335A2 Non-volatile memory and its sensing method |
| 12/28/2005 | EP1046121B1 Automatic test process with non-volatile result table store |
| 12/28/2005 | EP0860017B1 Loosely coupled mass storage computer cluster |
| 12/28/2005 | CN1714344A Electronic memory component or memory module, and method of operating same |
| 12/28/2005 | CN1714296A Application specific event based semiconductor memory test system |
| 12/28/2005 | CN1713302A Converting circuit for preventing from fault of correcting code |
| 12/28/2005 | CN1713301A Method and its circuit for correcting fast flashing EEPROM overerase |
| 12/27/2005 | US6981199 Method for arranging data output by semiconductor testers to packet-based devices under test |
| 12/27/2005 | US6981198 Dynamic error correction code shortening |
| 12/27/2005 | US6981196 Data storage method for use in a magnetoresistive solid-state storage device |
| 12/27/2005 | US6981191 ASIC logic BIST employing registers seeded with differing primitive polynomials |
| 12/27/2005 | US6981190 Controlling the content of specific desired memory elements when testing integrated circuits using sequential scanning techniques |
| 12/27/2005 | US6981188 Non-volatile memory device with self test |
| 12/27/2005 | US6981187 Test mode for a self-refreshed SRAM with DRAM memory cells |
| 12/27/2005 | US6981179 Microcomputer having built-in nonvolatile memory and check system thereof and IC card packing microcomputer having built-in nonvolatile memory and check system thereof |
| 12/27/2005 | US6981175 Memory and method for employing a checksum for addresses of replaced storage elements |
| 12/27/2005 | US6981067 External storage subsystem |
| 12/27/2005 | US6981066 External storage subsystem |
| 12/27/2005 | US6980478 Zero-enabled fuse-set |
| 12/27/2005 | US6980476 Memory device with test mode for controlling of bitline sensing margin time |
| 12/27/2005 | US6980475 Semiconductor memory device |
| 12/27/2005 | US6980461 Reference current generator, and method of programming, adjusting and/or operating same |
| 12/27/2005 | US6980036 Semiconductor device comprising frequency multiplier of external clock and output buffer of test data and semiconductor test method |
| 12/22/2005 | WO2005122181A1 Method and apparatus for interfacing between test system and embedded memory on test mode setting operation |
| 12/22/2005 | WO2005122180A1 Method for inspecting semiconductor memory |
| 12/22/2005 | WO2005122179A1 System and method for testing a data storage device without revealing memory content |
| 12/22/2005 | WO2005121961A2 Memory hub tester interface and method for use thereof |
| 12/22/2005 | US20050283713 Motion compensation method for video sequence encoding in low bit rate systems |
| 12/22/2005 | US20050283706 Method for changing a depth of an interleaver device or de-interleaver device and corresponding interleaver device and de-interleaver device |
| 12/22/2005 | US20050283688 Method and apparatus for testing a memory array |
| 12/22/2005 | US20050283681 Memory hub tester interface and method for use thereof |
| 12/22/2005 | US20050283671 Real time testing using on die termination (ODT) circuit |
| 12/22/2005 | US20050283657 Semiconductor memory device |
| 12/22/2005 | US20050283566 Self testing and securing ram system and method |
| 12/22/2005 | US20050281118 Integrated semiconductor memory comprising at least one word line and comprising a multiplicity of memory cells |
| 12/22/2005 | US20050281115 On-chip EE-PROM programming waveform generation |