Patents
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
05/2006
05/04/2006US20060092728 Circuit and method for test mode entry of a semiconductor memory device
05/04/2006US20060092727 Flood mode implementation for continuous bitline local evaluation circuit
05/04/2006US20060092726 Memory redundancy programming
05/04/2006US20060092725 Redundancy circuit and repair method for a semiconductor memory device
05/04/2006US20060092724 Semiconductor memory device with MOS transistors each having floating gate and control gate
05/04/2006DE19543834B4 Defektzellen-Reparaturschaltkreis und Defektzellen-Reparaturverfahren für eine Halbleiterspeichervorrichtung Defective cell repair circuit defect cells and repairing method for a semiconductor memory device
05/04/2006DE102005051308A1 Test procedure for memory device e.g. for microprocessor system, includes central device configured to receive memory control information
05/04/2006DE102005050394A1 Simulieren einer Bedingung einer floatenden Wortleitung in einer Speichervorrichtung und verwandte Techniken Simulating a condition of a floating word line in a memory device and related techniques
05/04/2006DE102005046697A1 Integrated semiconductor memory e.g. DRAM, has data- and address-terminals driven via supply lines
05/04/2006DE102004052594B3 Integrierter Halbleiterspeicher Integrated semiconductor memory
05/04/2006DE102004051346A1 Halbleiter-Bauelement-Test-Einrichtung, insbesondere Daten-Zwischenspeicher-Bauelement mit Halbleiter-Bauelement-Test-Einrichtung, sowie Halbleiter-Bauelement-Test-Verfahren Semiconductor device testing apparatus, in particular data latch device having semiconductor device testing apparatus, and semiconductor device testing method
05/04/2006DE102004051345A1 Halbleiter-Bauelement, sowie Verfahren zum Ein- und/oder Ausgeben von Testdaten A semiconductor device, and method for mounting and / or outputting of test data
05/04/2006DE102004051344A1 Semiconductor-component test device e.g. for testing integrated computing circuits, uses shift register with additional memory device for tapping further pseudo-random value
05/03/2006EP1653374A2 Method and apparatus for coordinating memory operations among diversely-located memory components
05/03/2006CN1768330A A high reliability memory module with a fault tolerant address and command bus
05/03/2006CN1767072A Error detecting memory module and method
05/03/2006CN1767069A Nonvolatile memory devices and methods of verifying data in nonvolatile memory devices
05/03/2006CN1767054A Memory device
05/03/2006CN1767053A Semiconductor storage device and method of testing thereof
05/02/2006US7039848 Data recording medium, data recording method and apparatus, data playback method and apparatus, and data determination method
05/02/2006US7039847 Coding-decoding device and method for conversion of binary sequences
05/02/2006US7039843 Modeling custom scan flops in level sensitive scan design
05/02/2006US7039838 Method for testing a circuit unit to be tested and test apparatus
05/02/2006US7039782 Memory system with channel multiplexing of multiple memory devices
05/02/2006US7039545 Apparatus, system and/or method for converting a serial test to a parallel test
05/02/2006US7038969 Semiconductor memory having a spare memory cell
05/02/2006US7038957 Semiconductor memory device for testifying over-driving quantity depending on position
05/02/2006US7038956 Apparatus and method for reading out defect information items from an integrated chip
05/02/2006US7038955 Semiconductor device and testing apparatus for semiconductor device
05/02/2006US7038949 Non-volatile memory device capable of changing increment of program voltage according to mode of operation
05/02/2006US7038925 Static semiconductor memory device having T-type bit line structure
05/02/2006US7038523 Voltage trimming circuit
05/02/2006US7038481 Method and apparatus for determining burn-in reliability from wafer level burn-in
05/02/2006US7038469 Method of determining localized electron tunneling in a capacitive structure
04/2006
04/27/2006US20060090117 Method And Related Apparatus For Data Error Checking
04/27/2006US20060090108 Method and apparatus for testing a memory device with compressed data using a single output
04/27/2006US20060090107 Semiconductor device
04/27/2006US20060090106 Generalized BIST for multiport memories
04/27/2006US20060090105 Built-in self test for read-only memory including a diagnostic mode
04/27/2006US20060090104 Adapting RCU for real-time operating system usage
04/27/2006US20060087307 Single pin multilevel integrated circuit test interface
04/27/2006DE20221512U1 Memory system for data processor, has differential signaling data bus with symbol time lesser than specific address and control bus symbol time
04/27/2006DE102004050104A1 Halbleiter-Bauelement, sowie Verfahren zum Auslesen von Testdaten A semiconductor device, and method of reading test data
04/27/2006DE102004022327B4 Integrierter Halbleiterspeicher Integrated semiconductor memory
04/26/2006CN1253724C Circuit arrangement for detecting malfunction
04/26/2006CN1253723C Device for indicating capacity and method for measuring capacity
04/25/2006US7036068 Error correction coding and decoding in a solid-state storage device
04/25/2006US7036058 Semiconductor device having integrally sealed integrated circuit chips arranged for improved testing
04/25/2006US7036057 Range splitting read/write methods for CD-MRW
04/25/2006US7036056 Semiconductor memory device having time reduced in testing of memory cell data reading or writing, or testing of sense amplifier performance
04/25/2006US7036055 Arrangements for self-measurement of I/O specifications
04/25/2006US7036054 Memory bus checking procedure
04/25/2006US7036053 Two dimensional data eye centering for source synchronous data transfers
04/25/2006US7035751 Nonvolatile memory microcomputer chip, and a method for testing the nonvolatile memory microcomputer chip
04/25/2006US7035164 Semiconductor memory device with a bypass circuit for verifying the characteristics of an internal clock signal
04/25/2006US7035159 Techniques for storing accurate operating current values
04/25/2006US7035158 Semiconductor memory with self fuse programming
04/25/2006US7035154 Semiconductor memory device and its test method as well as test circuit
04/25/2006US7035153 Semiconductor memory device of bit line twist system
04/25/2006US7035142 Non volatile memory device including a predetermined number of sectors
04/25/2006US7035137 Semiconductor memory device having memory cells including ferromagnetic films and control method thereof
04/25/2006US7035131 Dynamic random access memory cell leakage current detector
04/25/2006US7034564 Method for universally testing semiconductor devices with different pin arrangement
04/25/2006US7034560 Device and method for testing integrated circuit dice in an integrated circuit module
04/20/2006WO2006042058A2 Memory regulator system with test mode
04/20/2006WO2006040900A1 Testing device and testing method for testing object memory storing data raw with error correcting codes added
04/20/2006WO2005015569A3 Hub module for connecting one or more memory devices, comprising an address decoder unit for addressing redundant memory areas
04/20/2006US20060085705 Memory circuit comprising an initialization unit, and method for optimizing data reception parameters in a memory controller
04/20/2006US20060085704 Semi-conductor component, as well as a process for the reading of test data
04/20/2006US20060085703 Memory cell test circuit for use in semiconductor memory device and its method
04/20/2006US20060085702 Integrated circuit fuses having corresponding storage circuitry
04/20/2006US20060085701 Method and apparatus for separating native, functional and test configurations of memory
04/20/2006US20060085700 Decoder based set associative repair cache systems and methods
04/20/2006US20060085589 Status register to improve initialization of a synchronous memory
04/20/2006US20060083090 Method and apparatus for identifying short circuits in an integrated circuit device
04/20/2006US20060083089 Non-volatile memory with test rows for disturb detection
04/20/2006US20060083088 Spintronic devices with integrated transistors
04/20/2006US20060083087 Apparatus and method for semiconductor device repair with reduced number of programmable elements
04/20/2006US20060083086 Memory circuit with redundant memory cell array allowing simplified shipment tests and reduced power consumptions
04/20/2006US20060083085 Integrated circuit device and testing method thereof
04/20/2006US20060083084 Semiconductor test system
04/20/2006US20060083063 Memory devices with page buffer having dual registers and method of using the same
04/20/2006US20060083061 Flash cell fuse circuit
04/20/2006US20060083049 Ferroelectric memory
04/20/2006DE10338678B4 Vorrichtung und Verfahren zum Testen von zu testenden Schaltungseinheiten Apparatus and method for testing the circuit under test units
04/19/2006EP1647992A1 Memory circuit with a substitution memory for faulty memory cells
04/19/2006EP1647990A1 Method for refreshing a dynamic RAM, and corresponding dynamic RAM device, in particular incorporated in a cellular mobile telephone
04/19/2006EP1647882A2 Disk array system
04/19/2006EP1647031A1 Memory device and method of storing fail addresses of a memory cell
04/19/2006CN1762028A Memory system having fast and slow data reading mechanisms
04/19/2006CN1760987A Memory cell test circuit for use in semiconductor memory device and its method
04/19/2006CN1760838A Data detection system and method of read only memory in basic input/output system
04/19/2006CN1252807C Apparatus for testing integrated module and method for operating the testing device
04/19/2006CN1252730C Storage circuit with test compression function
04/19/2006CN1252727C Thin film magnetic storing device containing storage unit with magnetic tunnel junction
04/19/2006CN1252724C Self-detecting of magnetic-resistance memory array
04/18/2006US7032196 Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device
04/18/2006US7032158 System and method for recognizing and configuring devices embedded on memory modules
04/18/2006US7032157 Method for optimizing UDMA transfer signals using CRC errors
04/18/2006US7032144 Method and apparatus for testing multi-port memories