| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 06/08/2006 | US20060123282 Service layer architecture for memory access system and method |
| 06/08/2006 | US20060123281 Method and timing harness for system level static timing analysis |
| 06/08/2006 | US20060123280 Test circuit and method for multilevel cell flash memory |
| 06/08/2006 | US20060123279 Apparatus, system, and method for identifying fixed memory address errors in source code at build time |
| 06/08/2006 | US20060123222 Techniques for storing accurate operating current values |
| 06/08/2006 | US20060123221 Techniques for storing accurate operating current values |
| 06/08/2006 | US20060121650 Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of a semiconductor device |
| 06/08/2006 | US20060120188 Defect detection circuit |
| 06/08/2006 | US20060120187 Method and apparatus for semiconductor device repair with reduced number of programmable elements |
| 06/08/2006 | US20060120186 Semiconductor memory device with shift redundancy circuits |
| 06/08/2006 | US20060120185 System and method for configuring an integrated circuit |
| 06/08/2006 | US20060120168 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used |
| 06/08/2006 | US20060120154 Structure for testing nand flash memory and method of testing nand flash memory |
| 06/08/2006 | US20060120150 Thin-film magnetic memory device with memory cells having magnetic tunnel junction |
| 06/08/2006 | US20060120135 Semiconductor memory device |
| 06/08/2006 | US20060118774 Multiple bit chalcogenide storage device |
| 06/08/2006 | DE19922786B4 Halbleiterspeicher mit Testeinrichtung A semiconductor memory device with test |
| 06/08/2006 | DE102005025216A1 Testing method for dual in-line memory module, involves comparing data stored in address of memory, with expected data provided to hub of memory module |
| 06/08/2006 | DE102004057819A1 Input circuit for an integrated circuit esp. a circuit operating in burn in mode to preage the circuit so that it can operate normally after the burn in process |
| 06/08/2006 | DE102004057489A1 Verfahren und System zum Durchführen eines Prozesses an einem integrierten Schaltkreis Method and system for performing a process on an integrated circuit |
| 06/08/2006 | DE10103060B4 Verfahren zum Testen einer ein Floating-Gate aufweisenden Speicherzelle und Anordnung zur Durchführung dieses Verfahrens A method for testing a floating gate having a memory cell and device for carrying out this method |
| 06/08/2006 | DE10034851B4 Schaltungsanordnung zur Erzeugung von Steuersignalen zum Test hochfrequenter synchroner Digitalschaltungen Circuit arrangement for generating control signals for testing digital circuits of high-frequency synchronous |
| 06/08/2006 | DE10034850B4 System zum Test integrierter digitaler Halbleiterbauelemente A system for testing integrated digital semiconductor devices |
| 06/08/2006 | CA2589360A1 Memory system with sector buffers |
| 06/07/2006 | EP1665404A2 Multiple bit chalcogenide storage device |
| 06/07/2006 | EP1665287A1 Management of defective blocks in flash memories |
| 06/07/2006 | EP1665286A1 Integrated circuit and a method of cache remapping |
| 06/07/2006 | EP1665285A2 Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance |
| 06/07/2006 | EP1665283A1 Nonvolatile semiconductor memory device having protection function for each memory block |
| 06/07/2006 | EP1664808A2 Integrated circuit with test pad structure and method of testing |
| 06/07/2006 | EP1374250B1 Memory cell structural test |
| 06/07/2006 | EP1086469B1 Method and system for authenticating digital optical media |
| 06/07/2006 | CN1783347A Circuit and method for test mode entry of a semiconductor memory device |
| 06/07/2006 | CN1258771C Semiconductor memory |
| 06/07/2006 | CN1258770C Semiconductor integral circuit device |
| 06/07/2006 | CN1258769C Semiconductor storage device reading data according to current passing through storage unit while accessing |
| 06/06/2006 | US7058911 Measurement of timing skew between two digital signals |
| 06/06/2006 | US7058875 Method of correcting data on a high-density recording medium |
| 06/06/2006 | US7058865 Apparatus for testing semiconductor integrated circuit |
| 06/06/2006 | US7058864 Test for processor memory cache |
| 06/06/2006 | US7058863 Semiconductor integrated circuit |
| 06/06/2006 | US7058856 Semiconductor circuit with flash ROM and improved security for the contents thereof |
| 06/06/2006 | US7058851 Integrated memory and method of repairing an integrated memory |
| 06/06/2006 | US7058782 Method and apparatus for coordinating dynamic memory deallocation with a redundant bit line steering mechanism |
| 06/06/2006 | US7058756 Circuit for implementing special mode in packet-based semiconductor memory device |
| 06/06/2006 | US7058533 Calibration of memory circuits |
| 06/06/2006 | US7057967 Multi-mode synchronous memory device and methods of operating and testing same |
| 06/06/2006 | US7057951 Semiconductor memory device for controlling write recovery time |
| 06/06/2006 | US7057948 Semiconductor integrated circuit device having a test function |
| 06/06/2006 | US7057947 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used |
| 06/06/2006 | US7057946 Semiconductor integrated circuit having latching means capable of scanning |
| 06/06/2006 | US7057441 Block selection circuit |
| 06/06/2006 | US7057217 Fuse arrangement and integrated circuit device using the same |
| 06/06/2006 | US7056752 Fabricating a die with test enable circuits between embedded cores |
| 06/01/2006 | WO2006057963A2 Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding |
| 06/01/2006 | WO2006057794A2 Transparent error correcting memory that supports partial-word write |
| 06/01/2006 | WO2006057793A2 Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory |
| 06/01/2006 | WO2006056902A1 Sram test method and sram test arrangement to detect weak cells |
| 06/01/2006 | WO2005043276A3 System-in-package and method of testing thereof |
| 06/01/2006 | WO2004015717A3 Various methods and apparatuses to track failing memory locations to enable implementations for invalidating repeatedly failing memory locations |
| 06/01/2006 | US20060117242 Methods and devices for defect and reallocation management on write-once media |
| 06/01/2006 | US20060117241 Method and apparatus for managing disc defects |
| 06/01/2006 | US20060117231 Adaptive communication interface |
| 06/01/2006 | US20060117151 Method of verifying a system in which a plurality of master devices share a storage region |
| 06/01/2006 | US20060114738 Non-volatile semiconductor memory device |
| 06/01/2006 | US20060114732 Semiconductor device |
| 06/01/2006 | US20060114731 Method and apparatus for controlling a high voltage generator in a wafer burn-in test |
| 06/01/2006 | US20060114729 Non-volatile semiconductor memory device and memory system using the same |
| 06/01/2006 | US20060114726 Nonvolatile memory |
| 06/01/2006 | US20060113289 High-speed, precision, laser-based method and system for processing material of one or more targets within a field |
| 06/01/2006 | DE102005054898A1 Flexibles internes Adresszählverfahren und -vorrichtung Flexible internal Adresszählverfahren and apparatus |
| 06/01/2006 | DE102005028631A1 Page buffer for flash memory device, has n-type metaloxide semiconductor (NMOS) transistor that transfers data from cache latch to main latch, and secondary NMOS transistor that programs data in main latch according to program signal |
| 06/01/2006 | DE102004057532A1 Semiconductor chip e.g. memory chip, testing method, involves providing test logic, testing chip when test mode is set, issuing test results and/or status of test mode, and selecting test result and status of mode through serial bit strands |
| 05/31/2006 | EP1662511A1 Test of a decoder of non-volatile memory addresses |
| 05/31/2006 | CN1779865A Memory test circuit and method |
| 05/31/2006 | CN1779864A Method and device for verifying initialized state of nonvolatile memory device |
| 05/31/2006 | CN1779863A Method for producing bit-map information automatically during process of memory test |
| 05/31/2006 | CN1779648A Method for inspecting fault code in data |
| 05/31/2006 | CN1258190C Method for identifying integrated circuit |
| 05/30/2006 | US7055083 Method and apparatus for allocating CRC codes in a flash ROM |
| 05/30/2006 | US7055082 Information recording and reproducing apparatus |
| 05/30/2006 | US7055081 System and method for multi-channel decoding error correction |
| 05/30/2006 | US7055076 Output data compression scheme using tri-state |
| 05/30/2006 | US7055075 Apparatus for random access memory array self-test |
| 05/30/2006 | US7055074 Device to inhibit duplicate cache repairs |
| 05/30/2006 | US7055054 Fail-over of multiple memory blocks in multiple memory modules in computer system |
| 05/30/2006 | US7054788 Memory defect remedy analyzing method and memory test instrument |
| 05/30/2006 | US7054705 Method of manufacturing semiconductor devices |
| 05/30/2006 | US7054213 Method and circuit for determining sense amplifier sensitivity |
| 05/30/2006 | US7054209 Semiconductor memory device and test method thereof |
| 05/30/2006 | US7054208 Method and device for testing a sense amp |
| 05/30/2006 | US7054207 Method and system for selecting redundant rows and columns of memory cells |
| 05/30/2006 | US7054206 Sub-column-repair-circuit |
| 05/30/2006 | US7053686 Data strobe circuit using clock signal |
| 05/30/2006 | US7053647 Method of detecting potential bridging effects between conducting lines in an integrated circuit |
| 05/26/2006 | WO2006055862A2 Programmable memory built-in-self-test (mbist) method and apparatus |
| 05/25/2006 | US20060109726 Method, apparatus, and computer program product for implementing enhanced dram interface checking |
| 05/25/2006 | US20060109725 Apparatus and method for managing bad blocks in a flash memory |
| 05/25/2006 | US20060109724 Memory device capable of changing data output mode |
| 05/24/2006 | EP1659591A2 Semiconductor memory |