Patents
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
10/2006
10/24/2006US7126326 Semiconductor device testing apparatus, semiconductor device testing system, and semiconductor device testing method for measuring and trimming the output impedance of driver devices
10/24/2006US7126196 Self-testing printed circuit board comprising electrically programmable three-dimensional memory
10/24/2006US7126154 Test structure for a single-sided buried strap DRAM memory cell array
10/24/2006CA2212089C Bist memory test system
10/19/2006WO2006108755A1 Method and system for storing logical data blocks into flash-blocks in multiple non-volatile memories which are connected to at least one common data i/o bus
10/19/2006WO2006058892A3 Memory system with sector buffers
10/19/2006US20060236209 Logic integrated circuit having dynamic substitution function, information processing apparatus using the same, and dynamic substitution method of logic integrated circuit
10/19/2006US20060236208 Soft error correction method, memory control apparatus and memory system
10/19/2006US20060236207 Error detection, documentation, and correction in a flash memory device
10/19/2006US20060236206 Semiconductor memory device
10/19/2006US20060236205 Storage control circuit, and method for address error check in the storage control circuit
10/19/2006US20060236204 Memory device with serial transmission interface and error correction mehtod for serial transmission interface
10/19/2006US20060236201 High reliability memory module with a fault tolerant address and command bus
10/19/2006US20060236166 Integrated circuit capable of error management
10/19/2006US20060236165 Managing memory health
10/19/2006US20060236164 Automatic test entry termination in a memory device
10/19/2006US20060236163 Semiconductor memory component and method for testing semiconductor memory components having a restricted memory area
10/19/2006US20060236162 Method and system for performing system-level correction of memory errors
10/19/2006US20060236161 Apparatus and method for controlling disk array with redundancy
10/19/2006US20060236160 Mutli-layered information recording medium, reproduction apparatus, recording apparatus, reproduction method, and recording method
10/19/2006US20060233032 Non-volatile semiconductor memory device
10/19/2006DE19947827B4 Verfahren zum Speichern und Aufrechterhalten von Daten und Computer-Programm sowie Speichermedium damit A method for storing and maintaining data and computer program and storage medium so
10/19/2006DE102006010743A1 Speicherungselement zum Vermindern von Soft-Errors bei einer Logik Storage element for reducing soft errors in logic
10/19/2006DE102006008504A1 Direktzugriffsspeicher mit selektiver Aktivierung einer Auswahlleitung Random access memory with selective activation of a select line
10/19/2006DE102005016801A1 Verfahren und Rechnereinheit zur Fehlererkennung und Fehlerprotokollierung in einem Speicher Method and computer unit for error detection and error logging in a memory
10/18/2006EP1713085A1 Automated wear leveling in non-volatile storage systems
10/18/2006EP1712985A1 Method and system for storing logical data blocks into flash-blocks in multiple non-volatile memories which are connected to at least one common data I/O bus
10/18/2006EP1350254B1 Method for reading semiconductor die information in a parallel test and burn-in system
10/18/2006CN1849671A Management of defective blocks in flash memories
10/18/2006CN1848301A Test mode for detecting a floating word line
10/17/2006US7124348 Data storage method with error correction
10/17/2006US7124347 Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture
10/17/2006US7124339 Scan path circuit and semiconductor integrated circuit comprising the scan path circuit
10/17/2006US7124337 Data storage apparatus and method for handling data on a data storage apparatus
10/17/2006US7124336 Method for the defect analysis of memory modules
10/17/2006US7124325 Method and apparatus for internally trimming output drivers and terminations in semiconductor devices
10/17/2006US7123538 Semiconductor memory device for improving access time in burst mode
10/17/2006US7123528 Flash memory device having column predecoder capable of selecting all column selection transistors and stress test method thereof
10/17/2006US7123527 Redundancy fuse circuit
10/17/2006US7123526 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used
10/17/2006US7123519 Storage device employing a flash memory
10/17/2006US7123514 Memory device for improved reference current configuration
10/17/2006US7123512 Contiguous block addressing scheme
10/17/2006US7123502 Storage circuit, semiconductor device, and electronic apparatus
10/17/2006US7123501 Semiconductor memory device using ferroelectric capacitor, and semiconductor device with the same
10/17/2006US7123043 Method and apparatus for testing driver circuits of AMOLED
10/12/2006US20060230330 Device and method for recording information
10/12/2006US20060230328 Device and method for recording information
10/12/2006US20060230327 Apparatus for and method of recording digital information signals
10/12/2006US20060230325 Information recording and reproducing apparatus
10/12/2006US20060227636 Methods and systems for providing paper based outcomes
10/12/2006US20060227635 Methods and systems for providing paper based outcomes
10/12/2006US20060227634 Method for determining and classifying SRAM bit fail modes suitable for production test implementation and real time feedback
10/12/2006US20060227633 Internal voltage generator
10/12/2006US20060227632 Information processing system, information generating apparatus and method, information processing apparatus and method, and program
10/12/2006US20060227588 Semiconductor storage device
10/12/2006DE102006015376A1 Testmodus zum Erfassen einer Floating-Wortleitung Test mode for detecting a floating word line
10/12/2006DE102005016051A1 Speicherüberprüfungsvorrichtung und Verfahren zum Überprüfen eines Speichers Memory test device and method for checking a memory
10/12/2006DE102005016050A1 Semiconductor memory error detection device for use in motor vehicle electronics, has detecting unit that is designed for detecting error measure of memory when test parity value does not correspond to reference parity
10/11/2006CN1846278A Integrated circuit and a method of cache remapping
10/11/2006CN1845255A Semiconductor storage device
10/11/2006CN1845250A DRAM stacked package, DIMM, and semiconductor manufacturing method
10/11/2006CN1279614C Semiconductor device
10/10/2006US7120842 Mechanism to enhance observability of integrated circuit failures during burn-in tests
10/10/2006US7120841 Data generator for generating test data for word-oriented semiconductor memories
10/10/2006US7120777 Device identification using a memory profile
10/10/2006US7120773 Apparatus and method for memory management
10/10/2006US7120738 Storage system having data format conversion function
10/10/2006US7120729 Automated wear leveling in non-volatile storage systems
10/10/2006US7120086 Semiconductor circuit
10/10/2006US7120071 Test method for a semiconductor memory
10/10/2006US7120042 Ferroelectric memory device having test memory cell
10/10/2006US7119568 Methods for wafer level burn-in
10/05/2006WO2006104584A2 Memory having a portion that can be switched between use as data and use as error correction code (ecc)
10/05/2006WO2006102872A1 Electric system with defective memory areas and method for testing memory areas
10/05/2006US20060224936 Data transfer apparatus
10/05/2006US20060224933 Mechanism for implementing redundancy to mask failing SRAM
10/05/2006US20060221737 Data compression read mode for memory testing
10/05/2006US20060221736 Data compression read mode for memory testing
10/05/2006US20060221735 Semiconductor wafer and method for testing ferroelectric memory device
10/05/2006US20060221734 Detecting switching of access elements of phase change memory cells
10/05/2006US20060221733 Controller apparatus for utilizing downgrade memory and method for operating the same
10/05/2006US20060221732 Method and device for protecting a preamplifier in reading signals on a defect disc
10/05/2006US20060221731 Semiconductor integrated circuit device and inspection method of the same
10/05/2006US20060221730 Repair control circuit of semiconductor memory device with reduced size
10/05/2006US20060221729 Semiconductor memory device
10/05/2006US20060221728 Method and apparatus for incorporating block redundancy in a memory array
10/05/2006US20060221725 Semiconductor integrated circuit device
10/05/2006US20060221659 Access circuit and method for allowing external test voltage to be applied to isolated wells
10/05/2006US20060220680 Hardware and software programmable fuses for memory repair
10/05/2006DE102006004848A1 Verfahren und Vorrichtung zum Variieren eines aktiven Arbeitszyklus einer Wortleitung Method and apparatus for varying an active duty cycle of a word line
10/05/2006DE102005015319A1 Elektrisches System mit fehlerhaften Speicherbereichen und Verfahren zum Testen von Speicherbereichen Electrical system with faulty memory areas and method for testing memory areas
10/05/2006DE102005015002A1 Automatic repair method for integrated memory circuit using repair position data and fuses of integrated memory circuit, involves programming identified fuses using generated repair position data to repair integrated memory circuit
10/04/2006EP1708205A1 Ram testing apparatus and method
10/04/2006CN1842871A Accelerated life test of MRAM cells
10/04/2006CN1841567A Repair control circuit of semiconductor memory device with reduced size
10/04/2006CN1841566A Method for current sense amplifier calibration in MRAM devices
10/04/2006CN1841334A Storage control circuit, and method for address error check in the storage control circuit
10/04/2006CN1278421C Semiconductor devices
10/03/2006US7117428 Redundancy register architecture for soft-error tolerance and methods of making the same