G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation

Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
11/2006
11/30/2006	US20060271816 Device and method for configuring a cache tag in accordance with burst length
11/30/2006	US20060271590 Volume information analysis module and method thereof
11/30/2006	US20060268637 Input/output line sharing apparatus of semiconductor memory device
11/30/2006	US20060268636 Semiconductor device and entry into test mode without use of unnecessary terminal
11/30/2006	US20060268635 Nonvolatile semiconductor memory device
11/30/2006	US20060268634 Chip information managing method, chip information managing system, and chip information managing program
11/30/2006	US20060268633 Semiconductor device
11/30/2006	US20060268621 Method for programming a reference cell
11/30/2006	US20060268608 Data storage system
11/30/2006	US20060268605 Thin film magnetic memory device storing program information efficiently and stably
11/29/2006	EP1727156A2 An improved area efficient memory architecture with decoder self test and debug capability
11/29/2006	EP1727155A1 Semiconductor device
11/29/2006	EP1425594B1 Multilevel signal interface testing with binary test apparatus by emulation of multilevel signals
11/29/2006	CN1870178A 半导体器件 Semiconductor devices
11/29/2006	CN1869721A Chip information managing method, chip information managing system, and chip information managing program
11/28/2006	US7143371 Critical area computation of composite fault mechanisms using voronoi diagrams
11/28/2006	US7143331 Error correction apparatus for performing consecutive reading of multiple code words
11/28/2006	US7143327 Method and system for compressing repetitive data, in particular data used in memory device testing
11/28/2006	US7143326 Test system algorithmic program generators
11/28/2006	US7143325 Method for testing circuit units to be tested by means of majority decisions and test device for performing the method
11/28/2006	US7143321 System and method for multi processor memory testing
11/28/2006	US7143317 Computer event log overwriting intermediate events
11/28/2006	US7143303 Memory device for compensating for a clock skew causing a centering error and a method for compensating for the clock skew
11/28/2006	US7143229 Single-chip microcomputer with dynamic burn-in test function and dynamic burn-in testing method therefor
11/28/2006	US7142472 Semiconductor memory device and method for testing same
11/28/2006	US7142471 Method and apparatus for incorporating block redundancy in a memory array
11/28/2006	US7142469 Circuit for controlling an enabling time of an internal control signal according to an operating frequency of a memory device and the method thereof
11/28/2006	US7142457 Non-volatile semiconductor memory device
11/23/2006	WO2006124244A2 Redundant column read in a memory array
11/23/2006	US20060265636 Optimized testing of on-chip error correction circuit
11/23/2006	US20060265156 System and method for analyzing electrical failure data
11/23/2006	US20060262629 Semiconductor memory device capable of operating at high speed and with low power consumption while ensuring reliability of memory cell
11/23/2006	US20060262624 Method and architecture to calibrate read operatons in synchronous flash memory
11/23/2006	US20060262615 Semiconductor memory device
11/23/2006	US20060262614 Integrated circuit, test system and method for reading out an error datum from the integrated circuit
11/23/2006	US20060261839 Motherboard memory slot ribbon cable and apparatus
11/23/2006	DE102006007439A1 Verfahren und Vorrichtung zum Testen von Halbleitern unter Verwendung von Einzelchips mit integrierten Schaltungen A method and apparatus for testing semiconductors using single chips with integrated circuits
11/23/2006	DE102005014533A1 Unit testing and burning-in lower voltage semiconductors, memory, logic circuits and communications components, converts controller output to suitable voltage
11/23/2006	DE102004042072B4 Verfahren zum Testen einer zu testenden Schaltungseinheit und Testvorrichtung zur Durchführung des Verfahrens A method of testing a circuit under test unit and test device for carrying out the method
11/22/2006	EP1724788A1 Improved built-in self-test method and system
11/22/2006	EP1723571A2 Methods and apparatus for data analysis
11/22/2006	EP1582093A4 Improved patching methods and apparatus for fabricating memory modules
11/22/2006	CN1866399A Storage controller, involatile storage,involatile storage system and data inputting method
11/22/2006	CN1866390A Electric current type sensing apparatus and method for high-density multi-port cache
11/22/2006	CN1866389A Electric current type sensing apparatus and method for high-density multi-port cache
11/22/2006	CN1866223A Memory module, cache system and information apparatus
11/21/2006	US7139991 Automatic method and system for instantiating built-in-test (BIST) modules in ASIC memory designs
11/21/2006	US7139957 Automatic self test of an integrated circuit component via AC I/O loopback
11/21/2006	US7139956 Semiconductor integrated circuit device and test method thereof
11/21/2006	US7139951 Scan enabled storage device
11/21/2006	US7139946 Method and test circuit for testing memory internal write enable
11/21/2006	US7139945 Chip testing within a multi-chip semiconductor package
11/21/2006	US7139944 Method and system for determining minimum post production test time required on an integrated circuit device to achieve optimum reliability
11/21/2006	US7139943 Method and apparatus for providing adjustable latency for test mode compression
11/21/2006	US7139942 Method and apparatus for memory redundancy and recovery from uncorrectable errors
11/21/2006	US7139941 Method for correcting data using temporally preceding data
11/21/2006	US7139864 Non-volatile memory and method with block management system
11/21/2006	US7139847 Semiconductor memory device having externally controllable data input and output mode
11/21/2006	US7139209 Zero-enabled fuse-set
11/21/2006	US7139208 Refresh-free dynamic semiconductor memory device
11/21/2006	US7139204 Method and system for testing a dual-port memory at speed in a stressed environment
11/21/2006	US7139201 Non-volatile semiconductor memory device and memory system using the same
11/21/2006	US7138817 Method and apparatus for testing defective portion of semiconductor device
11/21/2006	US7138283 Method for analyzing fail bit maps of wafers
11/16/2006	WO2006121529A2 Method and apparatus for incorporating block redundancy in a memory array
11/16/2006	WO2006120951A1 Test device
11/16/2006	US20060259848 System and method for enhanced error detection in memory peripherals
11/16/2006	US20060256633 Handling defective memory blocks of NAND memory devices
11/16/2006	US20060256632 Method for analyzing defect of SRAM cell
11/16/2006	US20060256631 Internal data comparison for memory testing
11/16/2006	US20060256630 Apparatus and method to reduce undesirable effects caused by a fault in a memory device
11/16/2006	US20060256629 Defective block handling in a flash memory device
11/16/2006	US20060255823 Semiconductor device, method for testing the same and IC card
11/16/2006	DE102005060930A1 Speicheranwendungstester mit vertikal montierter Hauptplatine Memory Application Tester with vertically mounted motherboard
11/16/2006	DE10136548B4 Verfahren zum Prüfen interner Steuersignale in Halbleitervorrichtungen A method for testing internal control signals in semiconductor devices
11/15/2006	EP1438721B1 Semiconductor storage unit provided with intersecting word and bit lines whereon are arranged magnetoresistive memory cells
11/15/2006	EP1425593B1 Built-in self-testing of multilevel signal interfaces
11/15/2006	CN1864232A Error detection and correction method and apparatus in a magnetoresistive random access memory
11/15/2006	CN1864223A Method and apparatus for error code correction
11/15/2006	CN1862706A Volatile semiconductor memory
11/15/2006	CN1862500A Convolution-encoded raid with trellis-decode-rebuild
11/15/2006	CN1285111C Integrated circuit chip and wafer and its producing and detecting method
11/14/2006	US7137055 Semiconductor testing equipment, testing method for semiconductor, fabrication method of semiconductor, and semiconductor memory
11/14/2006	US7137051 Testing a multibank memory module
11/14/2006	US7137050 Compression circuit for testing a memory device
11/14/2006	US7137049 Method and apparatus for masking known fails during memory tests readouts
11/14/2006	US7137037 Data storage system and method for testing the same
11/14/2006	US7137027 Nonvolatile memory system
11/14/2006	US7136771 Semiconductor device and testing circuit which can carries out a verifying test effectively for non-volatile memory cells
11/14/2006	US7136318 Semiconductor memory device and circuit layout of dummy cell
11/14/2006	US7136316 Method and apparatus for data compression in memory devices
11/14/2006	US7136315 Bank selectable parallel test circuit and parallel test method thereof
11/14/2006	US7136313 Semiconductor storage device
11/14/2006	US7135882 Semiconductor integrated circuit device and control method for the semiconductor integrated circuit device
11/14/2006	CA2340633C Memory supervision
11/09/2006	US20060253750 Semiconductor integrated circuit and burn-in test method thereof
11/09/2006	US20060253749 Real-time memory verification in a high-availability system
11/09/2006	US20060253738 Real time testing using on die termination (ODT) circuit
11/09/2006	US20060250905 Data recording method for optical disk drive
11/09/2006	US20060250867 Adaptive algorithim for MRAM manufacturing

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