Patents
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
05/2007
05/02/2007EP1779251A1 Memory command delay balancing in a daisy-chained memory topology
05/02/2007EP1743431A4 File download and streaming system
05/02/2007EP1540478A4 Primary and remote data backup with nodal failover
05/02/2007CN1957424A Method for inspecting semiconductor memory
05/02/2007CN1956102A Semiconductor storage device
05/02/2007CN1956101A Method and system for processing defect in memory array
05/02/2007CN1314046C Storage controller, storage device and method with checking and erasing and correcting functions
05/01/2007US7213191 System and method for securely storing data in a memory
05/01/2007US7213186 Memory built-in self test circuit with full error mapping capability
05/01/2007US7213181 Recording medium having spare area for defect management and information of defect management, and method of allocating spare area and method of managing defects
05/01/2007US7213158 Distributed autonomic backup
05/01/2007US7213122 Controlling the generation and selection of addresses to be used in a verification environment
05/01/2007US7212456 Apparatus for dynamically repairing a semiconductor memory
05/01/2007US7212455 Decoder of semiconductor memory device
05/01/2007US7212454 Method and apparatus for programming a memory array
05/01/2007US7212453 Semiconductor memory having an error correction function
04/2007
04/26/2007WO2007047110A1 Corrected data storage and handling methods
04/26/2007WO2007046883A1 One-time programmable crosspoint memory with a diode as an antifuse
04/26/2007WO2007046491A1 Mram and its operation method
04/26/2007WO2007046350A1 Mram operation method
04/26/2007WO2007046349A1 Mram and its operation method
04/26/2007WO2007005218B1 Apparatus and method for repairing a semiconductor memory
04/26/2007US20070094574 Method and device for storing data
04/26/2007US20070094573 Method and device for error analysis of optical disc
04/26/2007US20070094572 Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method
04/26/2007US20070094571 ECC circuit of semiconductor memory circuit
04/26/2007US20070094570 Error detection in storage data
04/26/2007US20070094569 Determining hard errors vs. soft errors in memory
04/26/2007US20070094555 Component testing and recovery
04/26/2007US20070094554 Chip specific test mode execution on a memory module
04/26/2007US20070094553 Method of and apparatus for immediately writing or reading files on a disc-like recording medium having control information on defect management stored in a predefined location and such a disc-like recording medium
04/26/2007US20070094552 Method for accessing data of defected optical disk
04/26/2007US20070094551 Data storage apparatus and method for handling data on a data storage apparatus
04/26/2007US20070094550 Information recording device
04/26/2007US20070091706 Memory redundancy programming
04/26/2007US20070091698 Testing method and testing apparatus
04/26/2007US20070091697 Device recoverable purge for flash storage device
04/26/2007DE102006041817A1 Verfahren und Anordnung zum Testen eines Halbleiterbauelements mit gestapelten Einzelchips Method and apparatus for testing a semiconductor device with stacked dice
04/25/2007EP1451827A4 Dual mode high voltage power supply for providing increased speed in programming during testing of low voltage non-volatile memories
04/25/2007CN1954390A Repair of memory cells
04/25/2007CN1953102A Test data reporting and analyzing using data array and related data analysis
04/25/2007CN1952908A Accumulator with showing application progress and the method of showing application progress
04/24/2007US7210091 Recovering track format information mismatch errors using data reconstruction
04/24/2007US7210085 Method and apparatus for test and repair of marginally functional SRAM cells
04/24/2007US7210084 Integrated system logic and ABIST data compression for an SRAM directory
04/24/2007US7210079 Apparatus and method for adapting a level sensitive device to produce edge-triggered behavior
04/24/2007US7210078 Error bit method and circuitry for oscillation-based characterization
04/24/2007US7210077 System and method for configuring a solid-state storage device with error correction coding
04/24/2007US7210076 Interleaving order generator, interleaver, turbo encoder, and turbo decoder
04/24/2007US7210059 System and method for on-board diagnostics of memory modules
04/24/2007US7210016 Method, system and memory controller utilizing adjustable write data delay settings
04/24/2007US7210007 Method of verifying a system in which a plurality of master devices share a storage device
04/24/2007US7209997 Controller device and method for operating same
04/24/2007US7209591 Motion compensation method for video sequence encoding in low bit rate systems
04/24/2007US7209403 Enhanced fuse configurations for low-voltage flash memories
04/24/2007US7209398 Semiconductor memory device having redundancy cell array shared by a plurality of memory cell arrays
04/24/2007US7209397 Memory device with clock multiplier circuit
04/24/2007US7208759 Semiconductor integrated circuit device and method of testing the same
04/24/2007US7208758 Dynamic integrated circuit clusters, modules including same and methods of fabricating
04/24/2007US7208058 SOI substrate and manufacturing method thereof
04/19/2007WO2007044286A2 Memory scan testing
04/19/2007WO2006071937A3 System and method for efficient use of memory device bandwidth
04/19/2007WO2006026676A3 Seu-tolerant qdi circuits
04/19/2007US20070089035 Silent data corruption mitigation using error correction code with embedded signaling fault detection
04/19/2007US20070089034 Method of error correction in MBC flash memory
04/19/2007US20070089033 System and method of accessing non-volatile computer memory
04/19/2007US20070089032 Memory system anti-aliasing scheme
04/19/2007US20070089031 Methods and arrangements to remap degraded storage blocks
04/19/2007US20070088993 Memory tester having master/slave configuration
04/19/2007US20070086254 Integrated circuits with interchangeable connectors
04/19/2007US20070086253 Scanned memory testing of multi-port memory arrays
04/19/2007US20070086252 Semiconductor memory device
04/19/2007US20070085078 Semiconductor memory element and lifetime operation starting appartus therefor
04/19/2007DE10246741B4 Verfahren und Halbleitereinrichtung zum Abgleich von Schnittstelleneinrichtungen The method and semiconductor device for comparison of interface means
04/19/2007DE10243603B4 Verfahren zur Verwendung beim Trimmen, Halbleiter-Bauelement-Test-Gerät zum Durchführen des Verfahrens und Halbleiter-Bauelement-Test-System A method for use in trimming the semiconductor device test apparatus for performing the method and semiconductor device testing system
04/19/2007DE102004030602B4 Paralleler Datenbus und Verfahren zum Betreiben eines parallelen Datenbusses Parallel data bus and method for operating a parallel data bus
04/18/2007EP1483722B1 Memory module assembly using partially defective chips
04/18/2007CN1950910A 半导体存储器装置 The semiconductor memory device
04/18/2007CN1949396A Repairing circuit in semiconductor memory device
04/18/2007CN1311360C Memory controller with interlaced image memory mode
04/18/2007CN1311354C System for use in flash memory allowing bit alterability and method for data storage
04/17/2007US7206991 Method, apparatus and program for migrating between striped storage and parity striped storage
04/17/2007US7206990 Data sector error handling mechanism
04/17/2007US7206989 Integrated circuit having multiple modes of operation
04/17/2007US7206988 Error-correction memory architecture for testing production errors
04/17/2007US7206985 Method and apparatus for calibrating a test system for an integrated semiconductor circuit
04/17/2007US7206984 Built-in self test circuit and test method for storage device
04/17/2007US7206980 Integrated semiconductor memory
04/17/2007US7206979 Method and apparatus for at-speed diagnostics of embedded memories
04/17/2007US7206962 High reliability memory subsystem using data error correcting code symbol sliced command repowering
04/17/2007US7206897 Memory module having an integrated circuit buffer device
04/17/2007US7206896 Integrated circuit buffer device
04/17/2007US7206239 Semiconductor device and skew adjusting method
04/17/2007US7206238 Integrated semiconductor memory comprising at least one word line and method
04/17/2007US7206237 Apparatus and method for testing a memory device with multiple address generators
04/17/2007US7206236 Array redundancy supporting multiple independent repairs
04/12/2007WO2007041253A2 Motor and controller inversion: commanding torque to position-controlled robots
04/12/2007WO2007040569A2 System and method of accessing non-volatile computer memory
04/12/2007WO2006118775A3 Method and apparatus for transmitting data
04/12/2007US20070083800 System and method for varying test signal durations and assert times for testing memory devices