Patents
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
09/2013
09/25/2013CN103325423A Data automatically-comparing test circuit of non-volatile memory
09/25/2013CN103325422A SRAM timing sequence test circuit and test method
09/25/2013CN103325421A Non-volatile memory checkerboard test circuit and detection method thereof
09/25/2013CN103325420A Memory control circuit, method, and system
09/25/2013CN103325411A Single event upset resisting reinforcing system and method used for FPGA (Field Programmable Gate Array)
09/25/2013CN101697490B Decoding method applied to Reed-Solomon code-based ECC module
09/24/2013US8543874 Macro and command execution from memory array
09/24/2013US8543873 Multi-site testing of computer memory devices and serial IO ports
09/24/2013US8543863 Efficiency of hardware memory access using dynamically replicated memory
09/24/2013US8543801 Booting method using a backup memory in place of a failed main memory
09/24/2013US8542545 Repairing soft failures in memory cells in SRAM arrays
09/19/2013WO2013138190A1 Physical page, logical page, and codeword correspondence
09/19/2013WO2013138083A1 Error protection for memory devices
09/19/2013WO2013138028A1 Techniques for accessing column selecting shift register with skipped entries in non-volatile memories
09/19/2013WO2013137851A1 Distributed codeword portions
09/19/2013US20130246867 Test circuit, memory system, and test method of memory system
09/19/2013US20130242679 Semiconductor memory device for controlling write recovery time
09/18/2013CN103310853A Power supply switching circuit with built-in self test
09/18/2013CN103310852A MBIST (Memory Built In Self Test) controller structure system based on IEEE (Institute of Electrical and Electronics Engineers) 1500 standard and compatible with SRAM/ROM (Static Random Access Memory/Read Only Memory)
09/18/2013CN103310851A Self-repairing SRAM (Static Random Access Memory) controller design for DTMB (Digital Terrestrial Multimedia Broadcasting) demodulation chip
09/18/2013CN103310850A Built-in self-test structure and method for on-chip network resource node storage device
09/18/2013CN103310849A Test circuit, memory system, and test method of memory system
09/18/2013CN103310848A Method and apparatus using memory
09/18/2013CN102332309B DRAM (Dynamic Random Access Memory) source synchronization test method and circuit
09/18/2013CN101645310B Flash memory equipment, method and system for managing flash memory
09/17/2013US8539315 Semiconductor storage device, nonvolatile semiconductor memory test method, and medium
09/17/2013US8539313 System and method of data encoding
09/17/2013US8539311 System and method for data recovery in multi-level cell memories
09/17/2013US8539309 System and method for responding to error detection
09/17/2013US8539289 Memory testing system and method of computing device
09/17/2013US8539126 Capacitive multidrop bus compensation
09/17/2013US8537628 Test mode control circuit in semiconductor memory device and test mode entering method thereof
09/17/2013US8537601 Memory controller with selective data transmission delay
09/12/2013WO2013134071A1 Apparatuses and methods for combining error coding and modulation schemes
09/12/2013WO2013134066A1 Apparatuses and methods including error correction code organization
09/12/2013WO2013134053A1 Voltage mode sensing for low power flash memory
09/12/2013WO2013132806A1 Nonvolatile logic integrated circuit and nonvolatile register error bit correction method
09/12/2013WO2013132532A1 Semiconductor storage device having nonvolatile semiconductor memory
09/12/2013US20130235685 Semiconductor memory device and method of screening the same
09/12/2013US20130235677 Circuit for parallel bit test of semiconductor memory device
09/12/2013US20130235649 Direct relative measurement of memory durability
09/12/2013DE10197113B3 Verfahren zum Aktivieren eines speziellen Programmiermodus eines Speichers und Einrichtung mit einem Speicher mit speziellem Programmiermodus A method for activating a special programming mode of a memory device with a memory and with a special programming mode
09/12/2013DE10151609B4 Schaltung für einen elektronischen Halbleiterbaustein Circuit for an electronic semiconductor device
09/11/2013CN203192417U Reading-speed measuring circuit based on automatic and periodic reading operation
09/11/2013CN103295650A Test method, power supply device, power supply evaluation device and simulation method
09/11/2013CN103295649A Method for improving reliability of a nonvolatile memory
09/11/2013CN103295648A Storage device unit restoring device and method and storage device system comprising device
09/11/2013CN103295647A Data duplication method and device of memory array with redundancy memory
09/11/2013CN103295646A Built-in self-test circuit applied on high-speed output/input end
09/11/2013CN103295645A Scanning detection method and system for dynamic memory
09/11/2013CN103295644A 存储器装置 The memory device
09/10/2013US8533578 Error detection in a content addressable memory (CAM) and method of operation
09/10/2013US8533572 Error correcting code logic for processor caches that uses a common set of check bits
09/10/2013US8533571 Lossy coding of signals
09/10/2013US8533570 Magnetic recording apparatus
09/10/2013US8533569 Apparatus, system, and method for managing data using a data pipeline
09/10/2013US8533568 LDPC encoding methods and apparatus
09/10/2013US8533566 Method and apparatus for storing data
09/10/2013US8533565 Cache controller and cache controlling method
09/10/2013US8533563 Memory read-out
09/10/2013US8533562 Data protection after possible write abort or erase abort
09/10/2013US8533550 Method and system to improve the performance and/or reliability of a solid-state drive
09/10/2013US8533541 Verification support of circuit blocks having independent clock domains
09/06/2013WO2013130230A1 Saving of data in cases of word-line to word-line short in memory arrays
09/05/2013US20130232393 Error detection and correction codes for channels and memories with incomplete error characteristics
09/05/2013US20130232386 Memory devices, testing systems and methods
09/05/2013US20130232385 Latency Detection in a Memory Built-In Self-Test by Using a Ping Signal
09/05/2013US20130229886 Repair device and method for integrated circuit structured arrays
09/05/2013US20130229883 Systems, memories, and methods for repair in open digit memory architectures
09/05/2013US20130229877 Memory with bit line current injection
09/04/2013CN203179556U Non-welding in-circuit chip RAM (random access memory) detection system
09/04/2013CN103280243A Display method of memory multi-bit upset based on word line segmentation
09/04/2013CN103280242A Configurable background refreshing method suitable for performing EDAC (Error Detection And Correction) on on-chip memory
09/04/2013CN103280241A Test circuit and test method of memorizer
09/04/2013CN103280240A Detecting method of memory multi-bit upset based on word line segmentation
09/04/2013CN102306504B Sample collecting method and method for predicting health condition of copying equipment
09/04/2013CN101615433B Storage device and testing method thereof
09/03/2013US8527841 Apparatus, system, and method for using multi-level cell solid-state storage as reduced-level cell solid-state storage
09/03/2013US8527840 System and method for restoring damaged data programmed on a flash device
09/03/2013US8527839 On-the-fly repair method for memory
09/03/2013US8527837 Selective error control coding in memory devices
09/03/2013US8527836 Rank-specific cyclic redundancy check
09/03/2013US8527835 Method for secure data transfer
09/03/2013US8527820 Semiconductor device and test method thereof
09/03/2013US8527819 Data storage in analog memory cell arrays having erase failures
09/03/2013US8526254 Test cells for an unprogrammed OTP memory array
09/03/2013US8526253 Method of screening static random access memories for pass transistor defects
09/03/2013US8526252 Quiescent testing of non-volatile memory array
08/2013
08/29/2013WO2013126109A1 Temperature based compensation during verify operations for non-volatile storage
08/29/2013US20130227362 Systems and methods of using dynamic data for wear leveling in solid-state devices
08/29/2013US20130227361 Hardwired remapped memory
08/29/2013US20130227342 Systems and methods for storing and retrieving a defect map in a dram component
08/29/2013US20130223172 Self-repair integrated circuit and repair method
08/29/2013US20130223171 Semiconductor Device Capable of Rescuing Defective Characteristics Occurring After Packaging
08/29/2013US20130223170 Semiconductor memory device
08/29/2013US20130223168 Deeply pipelined integrated memory built-in self-test (bist) system and method
08/29/2013US20130223159 Memory with variable strength sense amplifier
08/29/2013DE102013101441A1 Memory system transfers error address detected by test apparatus to memory device, and stores detected error address in non volatile memory device
08/29/2013DE102013100030A1 Halbleitervorrichtung, die in der Lage ist, nach dem Häusen auftretende defekte Eigenschaften zu retten A semiconductor device which is able to save occurring after the defective housings properties
08/28/2013EP2631915A2 Programming a memory with varying bits per cell
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