Patents
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
07/2000
07/18/2000US6091076 Quantum WELL MOS transistor and methods for making same
07/18/2000US6090722 Doping; forming polymer
07/18/2000US6090716 Method of fabricating a field effect transistor
07/18/2000US6090693 Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors
07/18/2000US6090692 Fabrication method for semiconductor memory device
07/18/2000US6090691 Method for forming a raised source and drain without using selective epitaxial growth
07/18/2000US6090684 Method for manufacturing semiconductor device
07/18/2000US6090676 Process for making high performance MOSFET with scaled gate electrode thickness
07/18/2000US6090672 Ultra short channel damascene MOS transistors
07/18/2000US6090671 Reduction of gate-induced drain leakage in semiconductor devices
07/18/2000US6090670 Highly efficient transistor for fast programming of flash memories
07/18/2000US6090669 Growing lightly doped n-type epitaxial layer on heavily doped n-type substrate, growing oxide on upper portion of epitaxial layer, masking and doping boron ions, etching oxide to expose regions for aluminum doping; masking, thermal diffusion
07/18/2000US6090668 Method to fabricate sharp tip of poly in split gate flash
07/18/2000US6090667 Method of manufacturing floating gate type transistor
07/18/2000US6090666 Method for fabricating semiconductor nanocrystal and semiconductor memory device using the semiconductor nanocrystal
07/18/2000US6090665 Method of producing the source regions of a flash EEPROM memory cell array
07/18/2000US6090658 Method of forming a capacitor including a bottom silicon diffusion barrier layer and a top oxygen diffusion barrier layer
07/18/2000US6090654 Method for manufacturing a static random access memory cell
07/18/2000US6090652 Method of manufacturing a semiconductor device including implanting threshold voltage adjustment ions
07/18/2000US6090650 Method to reduce timing skews in I/O circuits and clock drivers caused by fabrication process tolerances
07/18/2000US6090649 Heterojunction field effect transistor and method of fabricating the same
07/18/2000US6090648 Provideing sapphire substrate with silicon layer; forming polysilicon layer over silicon layer; defining silicon island in first silicon layer; doping with desired conductivity determining material to form resistor region
07/18/2000US6090647 Capacitor for a semiconductor device
07/18/2000US6090646 Method for producing semiconductor device
07/18/2000US6090638 Process for manufacturing high-sensitivity capacitive and resonant integrated sensors, particularly accelerometers and gyroscopes, and sensors made therefrom
07/18/2000US6090443 Multi-layer approach for optimizing ferroelectric film performance
07/18/2000US6089093 Accelerometer and method for making same
07/18/2000US6089089 Multi-element micro gyro
07/13/2000WO2000041247A2 Quantum-size electronic devices and operating conditions thereof
07/13/2000WO2000041246A1 Semiconductor system with trenches for separating doped areas
07/13/2000WO2000041245A1 Quantum-size electronic devices and methods of operating thereof
07/13/2000WO2000041244A1 Semiconductor energy detector
07/13/2000WO2000041243A1 Field isolated integrated injection logic gate
07/13/2000WO2000020916A3 Nanoparticle-based electrical, chemical, and mechanical structures and methods of making same
07/13/2000DE19859502A1 Sperrschicht-Feldeffekttransistor mit höher dotiertem Verbindungsgebiet JFET with higher doped junction region
07/13/2000DE10000754A1 Semiconductor device with a multiple vertical p-n junction layer, e.g. a vertical MOSFET, IGBT, bipolar transistor or diode, is produced by ion implantation and heat treatment to form vertical drift zones or separation zones
07/12/2000EP1018769A2 Semiconductor device with increased gate insulator lifetime
07/12/2000EP1018758A1 Method for forming monocrystalline silicon layer, method for manufacturing semiconductor device, and semiconductor device
07/12/2000EP1018164A1 Silicon carbide static induction transistor structures
07/12/2000EP1018163A1 Semiconductor component with a drift zone
07/12/2000EP1018145A2 Microbellows actuator
07/12/2000EP0809865B1 SEMICONDUCTOR FIELD EFFECT DEVICE COMPRISING A SiGe LAYER
07/12/2000EP0800705B1 Manufacture of a semiconductor device with selectively deposited semiconductor zone
07/12/2000EP0739538B1 Method of forming a resistor
07/12/2000CN1260068A Latch-up free power mos-bipolar transistor
07/12/2000CN1259763A Semiconductor elements and mfg. method therefor
07/12/2000CN1054469C Method for forming semiconductor device
07/11/2000USRE36777 Integration of high performance submicron CMOS and dual-poly non-volatile memory devices using a third polysilicon layer
07/11/2000USRE36770 MOS-controlled high-power thyristor
07/11/2000US6088604 Superconductor-normal conductor junction device
07/11/2000US6088287 Flash memory architecture employing three layer metal interconnect for word line decoding
07/11/2000US6088263 Non-volatile memory using substrate electrons
07/11/2000US6088257 Ferroelectric random access memory device and method for operating the same
07/11/2000US6088072 Liquid crystal display having a bus line formed of two metal layers and method of manufacturing the same
07/11/2000US6088071 Auxiliary capacitor for a liquid crystal display device
07/11/2000US6087893 Semiconductor integrated circuit having suppressed leakage currents
07/11/2000US6087730 Electronic devices and their manufacture
07/11/2000US6087727 Misfet semiconductor device having different vertical levels
07/11/2000US6087721 Semiconductor device with a high-frequency bipolar transistor on an insulating substrate
07/11/2000US6087708 Semiconductor integrated circuit device and a method of producing the same
07/11/2000US6087706 Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls
07/11/2000US6087704 Structure and method for manufacturing group III-V composite Schottky contacts enhanced by a sulphur fluoride/phosphorus fluoride layer
07/11/2000US6087702 Rare-earth schottky diode structure
07/11/2000US6087701 Semiconductor device having a cavity and method of making
07/11/2000US6087700 Gate having a barrier of titanium silicide
07/11/2000US6087698 Semiconductor device and method of manufacturing the same
07/11/2000US6087697 Radio frequency power MOSFET device having improved performance characteristics
07/11/2000US6087696 Stacked tunneling dielectric technology for improving data retention of EEPROM cell
07/11/2000US6087695 Source side injection flash EEPROM memory cell with dielectric pillar and operation
07/11/2000US6087689 Memory cell having a reduced active area and a memory array incorporating the same
07/11/2000US6087688 Field effect transistor
07/11/2000US6087687 MISFET device with ferroelectric gate insulator
07/11/2000US6087685 Solid-state imaging device
07/11/2000US6087684 Bipolar transistor
07/11/2000US6087683 Silicon germanium heterostructure bipolar transistor with indium doped base
07/11/2000US6087679 Semiconductor thin film and semiconductor device
07/11/2000US6087678 Thin-film transistor display devices having composite electrodes
07/11/2000US6087675 Semiconductor device with an insulation film having emitter contact windows filled with polysilicon film
07/11/2000US6087648 Active matrix display device and method of manufacturing the same
07/11/2000US6087647 Solid state imaging device and driving method therefor
07/11/2000US6087580 Semiconductor having large volume fraction of intermediate range order material
07/11/2000US6087276 Method of making a TFT having an ion plated silicon dioxide capping layer
07/11/2000US6087272 Method of producing thin film transistor
07/11/2000US6087268 Forming gate electrode of boron-doped polysilicon over gate oxide, isotropically forming a nitride over gate electrode at low temperature, anisotropically etching the nitride to leave a nitride sidewall spacer adjacent the gate electrode
07/11/2000US6087256 Method for manufacturing modified T-shaped gate electrode
07/11/2000US6087249 Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation
07/11/2000US6087248 Method of forming a transistor having thin doped semiconductor gate
07/11/2000US6087246 Method for fabricating dual gate semiconductor device
07/11/2000US6087245 Method of gettering crystallization catalyst for forming a silicon film
07/11/2000US6087241 Method of forming side dielectrically isolated semiconductor devices and MOS semiconductor devices fabricated by this method
07/11/2000US6087237 Method of manufacturing a MOSFET by forming a single oxide layer doping with either an oxide accelerator or an oxide inhibitor producing asymmetric thickness
07/11/2000US6087235 Method for effective fabrication of a field effect transistor with elevated drain and source contact structures
07/11/2000US6087232 Forming drift region of second conductivity type in epitaxial layer of first conductivity type having silicon substrate; forming pad oxide, nitride pattern, field oxide, convex region, tapered top layer, tetraethoxy silane oxide pattern
07/11/2000US6087231 Fabrication of dual gates of field transistors with prevention of reaction between the gate electrode and the gate dielectric with a high dielectric constant
07/11/2000US6087230 Method of fabricating an SOI device having a channel with variable thickness
07/11/2000US6087229 Composite semiconductor gate dielectrics
07/11/2000US6087224 Manufacture of trench-gate semiconductor devices
07/11/2000US6087223 Method of fabricating flash memory with dissymmetrical floating gate
07/11/2000US6087219 Highly reliable flash memory structure with halo source
07/11/2000US6087215 Method of fabricating a DRAM device