Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
08/2000
08/09/2000EP1026753A2 Device and method for storing information
08/09/2000EP1026752A2 Semiconductor device and method for its preparation
08/09/2000EP1026751A2 Semiconductor device and method for its preparation
08/09/2000EP1026750A1 Insulated gate field-effect transistors
08/09/2000EP1026749A1 Semiconductor device and method for fabricating the same
08/09/2000EP1026746A2 Gain cell DRAM structure
08/09/2000EP1026738A2 Novel mixed voltage CMOS process for high reliability and high performance core and I/O transistors with reduced mask steps
08/09/2000EP1026737A2 A method for fabricating a merged integrated circuit device
08/09/2000EP1026733A1 Semiconductor device for use in a light valve device, and process for manufacturing the same
08/09/2000EP1025593A1 Semiconductor with tunnel hole contact sources
08/09/2000EP1025592A1 Semiconductor diode
08/09/2000EP1025591A1 Vertical mos transistor and method for the production thereof
08/09/2000EP1025570A2 Method for arrangement of a buried capacitor, and a buried capacitor arranged according to said method
08/09/2000EP1025449A1 Electron devices for single electron and nuclear spin measurement
08/09/2000EP0611484B1 PROCESS FOR PRODUCING A Si/FeSi2-HETEROSTRUCTURE
08/09/2000CN1262787A II-VI semiconductor component with at least one junction between Se-containing layer and BeTe containing layer and method for producing said junction
08/09/2000CN1262527A Dynamic RAM
08/09/2000CN1262525A Semiconductor device with common position contact zone
08/09/2000CN1055350C Slotted-form grid electrostatic inductor
08/08/2000US6101131 Flash EEPROM device employing polysilicon sidewall spacer as an erase gate
08/08/2000US6101130 Semiconductor device memory cell and method for selectively erasing the same
08/08/2000US6101124 Memory block for realizing semiconductor memory devices and corresponding manufacturing process
08/08/2000US6101123 Nonvolatile semiconductor memory with programming and erasing verification
08/08/2000US6101120 Semiconductor memory device
08/08/2000US6101117 Two transistor single capacitor ferroelectric memory
08/08/2000US6100954 Liquid crystal display with planarizing organic gate insulator and organic planarization layer and method for manufacturing
08/08/2000US6100950 Active matrix LCD with thin film transistor switches and method of producing the same
08/08/2000US6100949 Liquid crystal display device having electrostatic discharge protection
08/08/2000US6100947 Liquid crystal panel substrate, liquid crystal panel and electronic apparatus using the same
08/08/2000US6100770 MIS transistor varactor device and oscillator using same
08/08/2000US6100753 Bias stabilization circuit
08/08/2000US6100751 Forward body biased field effect transistor providing decoupling capacitance
08/08/2000US6100591 Semiconductor device and method of fabricating the same
08/08/2000US6100586 The electrical contact comprises a layer of p-type gallium nitride, a metal layer, and an intermediate layer sandwiched between above two layer and including layers of differnt group 3 to 5 semiconduictors with prefered energy levels
08/08/2000US6100580 Semiconductor device having all outer leads extending from one side of a resin member
08/08/2000US6100579 Insulating film for use in semiconductor device
08/08/2000US6100578 Silicon-based functional matrix substrate and optical integrated oxide device
08/08/2000US6100575 Semiconductor switching device having different carrier lifetimes between a first portion serving as a main current path and the remaining portion of the device
08/08/2000US6100572 Amorphous silicon combined with resurf region for termination for MOSgated device
08/08/2000US6100571 Fet having non-overlapping field control electrode between gate and drain
08/08/2000US6100570 Semiconductor device having a semiconductor film of low oxygen concentration
08/08/2000US6100566 Multi-layer semiconductor device and method for fabricating the same
08/08/2000US6100565 Semiconductor integrated circuit device with operation in partial depletion type mode and perfect depletion type mode
08/08/2000US6100563 Semiconductor device formed on SOI substrate
08/08/2000US6100562 Method of manufacturing a semiconductor device
08/08/2000US6100560 Nonvolatile cell
08/08/2000US6100558 Semiconductor device having enhanced gate capacitance by using both high and low dielectric materials
08/08/2000US6100555 Semiconductor device having a photosensitive organic film, and process for producing the same
08/08/2000US6100554 High-frequency semiconductor device
08/08/2000US6100552 Multi-tapped bi-directional CCD readout register
08/08/2000US6100549 High breakdown voltage resurf HFET
08/08/2000US6100547 Field effect type semiconductor device and method of fabricating the same
08/08/2000US6100542 The electron supply layer includes a doped superlattice layer which includes two dissimilar layers of indium aluminum arsenide which alternates with each other for generating a two-dimentional electron gas
08/08/2000US6100204 Forming a gate electrode on a dielectric layer of an aluminum oxide made by exposing the substrate to aluminum chloride and oxygen; forming first/second source/drain regions in the substrate separated to define a channel; transistors
08/08/2000US6100201 Method of forming a semiconductor memory device
08/08/2000US6100193 Method of manufacturing a semiconductor device
08/08/2000US6100189 Second implant for agglomeration control
08/08/2000US6100188 Stable and low resistance metal/barrier/silicon stack structure and related process for manufacturing
08/08/2000US6100174 GaN group compound semiconductor device and method for producing the same
08/08/2000US6100173 Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process
08/08/2000US6100172 Method for forming a horizontal surface spacer and devices formed thereby
08/08/2000US6100169 Methods of fabricating silicon carbide power devices by controlled annealing
08/08/2000US6100159 Quasi soi device
08/08/2000US6100153 Reliable diffusion resistor and diffusion capacitor
08/08/2000US6100152 Method of manufacturing a semiconductor device with a fast bipolar transistor
08/08/2000US6100151 Highly integrated bipolar junction transistors having trench-based emitter and base regions and methods of forming same
08/08/2000US6100148 Semiconductor device having a liner defining the depth of an active region, and fabrication thereof
08/08/2000US6100147 Method for manufacturing a high performance transistor with self-aligned dopant profile
08/08/2000US6100146 Method of forming trench transistor with insulative spacers
08/08/2000US6100143 Method of making a depleted poly-silicon edged MOSFET structure
08/08/2000US6100142 Method of fabricating sub-quarter-micron salicide polysilicon
08/08/2000US6100140 Manufacturing method of semiconductor device
08/08/2000US6100122 Thin film transistor having an insulating membrane layer on a portion of its active layer
08/08/2000US6100121 Method of fabricating a thin film transistor having a U-shaped gate electrode
08/08/2000US6100120 Method of locally forming a high-k dielectric gate insulator
08/08/2000US6100119 Thin film transistor and method for fabricating the same
08/08/2000US6100115 Semiconductor device
08/08/2000US6100111 Method for fabricating a silicon carbide device
08/08/2000US6100013 Depositing hybrid resist on the substrate, exposing the resist through a mask, developing the resist, forming gate sidewall spacer in hybrid resist, etching through hybrid resist sidewall spacer, blanket exposure and development
08/08/2000US6099945 Atomic mask and method of patterning a substrate with the atomic mask
08/08/2000US6099803 Devices containing active electrodes especially adapted for electrophoretic transport of nucleic acids, their hybridization and analysis
08/08/2000US6099640 Molecular beam epitaxial growth method
08/08/2000US6099574 Method and apparatus for obtaining structure of semiconductor devices and memory for storing program for obtaining the same
08/08/2000US6098278 Method for forming conductive epoxy flip-chip on chip
08/03/2000WO2000045441A2 Semiconductor device with a multiple dielectric
08/03/2000WO2000045439A1 Device providing protection against electrostatic discharges for microelectronic components on a soi-type substrate
08/03/2000WO2000045436A1 Method and apparatus for elimination of parasitic bipolar action in complementary oxide semiconductor (cmos) silicon on insulator (soi) circuits
08/03/2000WO2000045423A1 Method and apparatus for elimination of parasitic bipolar action in logic circuits
08/03/2000WO2000019509A3 Method of manufacturing a semiconductor device with a field effect transistor
08/03/2000DE19902749A1 Leistungstransistoranordnung mit hoher Spannungsfestigkeit Power transistor device with high electric strength
08/03/2000DE10003066A1 Semiconductor sensor, e.g. an acceleration, yaw rate or vibration sensor, has electrical insulators between a frame portion and a mobile or stationary electrode
08/03/2000DE10002121A1 Herstellung einer Halbleitervorrichtung mit flachen Sperrschichten Manufacturing a semiconductor device having flat barrier layers
08/02/2000EP1024538A1 MOS varactor, in particular for radio-frequency transceivers
08/02/2000EP1024537A2 Insulated gate field effect transistor having a buried region and method of making the same
08/02/2000EP1024534A2 Device comprising thermally stable, low dielectric constant material
08/02/2000EP1024528A2 Semiconductor device and method for manufacturing same
08/02/2000EP1024526A1 An integrated circuit device having a planar interlevel dielectric layer
08/02/2000EP1024525A1 Integrated power structure for radio-frequency applications
08/02/2000EP1024524A2 Deposition of dielectric layers using supercritical CO2
08/02/2000EP1023745A1 Reduction of gate-induced drain leakage in semiconductor devices
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