Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
10/2000
10/31/2000US6140678 Trench-gated power MOSFET with protective diode
10/31/2000US6140676 Semiconductor non-volatile memory device having an improved write speed
10/31/2000US6140675 Semiconductor device and manufacturing method thereof
10/31/2000US6140674 Buried trench capacitor
10/31/2000US6140673 Semiconductor memory device and fabricating method
10/31/2000US6140667 Semiconductor thin film in semiconductor device having grain boundaries
10/31/2000US6140251 Method of processing a substrate
10/31/2000US6140248 Process for producing a semiconductor device with a roughened semiconductor surface
10/31/2000US6140219 Method of forming contact openings
10/31/2000US6140213 Semiconductor wafer and method of manufacturing same
10/31/2000US6140205 Method of forming retrograde well in bonded waffers
10/31/2000US6140199 Method and arrangement of a buried capacitor, and a buried capacitor arranged according to said method
10/31/2000US6140195 Method for fabricating a lateral collector structure on a buried oxide layer
10/31/2000US6140194 Method relating to the manufacture of a semiconductor component
10/31/2000US6140193 Method for forming a high-voltage semiconductor device with trench structure
10/31/2000US6140190 Method and structure for elevated source/drain with polished gate electrode insulated gate field effect transistors
10/31/2000US6140189 Method for fabricating a LOCOS MOS device for ESD protection
10/31/2000US6140186 Method of forming asymmetrically doped source/drain regions
10/31/2000US6140182 Nonvolatile memory with self-aligned floating gate and fabrication process
10/31/2000US6140181 Memory using insulator traps
10/31/2000US6140173 Method of manufacturing a semiconductor device comprising a ferroelectric memory element
10/31/2000US6140171 FET device containing a conducting sidewall spacer for local interconnect and method for its fabrication
10/31/2000US6140169 Method for manufacturing field effect transistor
10/31/2000US6140167 High performance MOSFET and method of forming the same using silicidation and junction implantation prior to gate formation
10/31/2000US6140164 Method of manufacturing a semiconductor device
10/31/2000US6140161 Semiconductor integrated circuit device and method for making the same
10/31/2000US6140159 Method for activating an ohmic layer for a thin film transistor
10/31/2000US6140158 Method of manufacturing thin film transistor-liquid crystal display
10/31/2000US6140157 Memory device using movement of protons
10/31/2000US6140147 Method for driving solid-state imaging device
10/31/2000US6140143 Method of producing a buried boss diaphragm structure in silicon
10/31/2000US6140009 Heat exchangers for electroluminescent device formed by positioning the transfer layer on receptor substrate and heat exchanging
10/31/2000US6139628 Method of forming gallium nitride crystal
10/31/2000US6139483 Method of forming lateral resonant tunneling devices
10/31/2000US6138606 Ion implanters for implanting shallow regions with ion dopant compounds containing elements of high solid solubility
10/31/2000CA2107676C A single transistor non-volatile electrically alterable semiconductor memory device
10/26/2000WO2000063974A1 Semiconductor device providing overvoltage and overcurrent protection for a line
10/26/2000WO2000063972A1 Semiconductor component
10/26/2000DE19961061A1 Semiconductor device for switching has silicon on insulator construction with MOS transistor circuit configuration
10/26/2000DE19960234A1 Diode manufacturing method, has buried p semiconductor barrier which is provided at head surface of semiconductor substrate.
10/26/2000DE19953178A1 Millimeter band semiconductor circuit for microwave transmission and radar systems, has field effect transistor switching element between transmission line and earth
10/26/2000DE19929210C1 Substrate used as a SOI substrate comprises a layer of monocrystalline silicon, a silicon dioxide layer and a silicon substrate
10/26/2000DE10013013A1 Chemical synthesized components, intersects pair of crossing conductors which form crossing which has function for measurement in nanometer range
10/25/2000EP1047135A2 Fast turn-off power semiconductor devices
10/25/2000EP1047133A1 Method for producing devices for control circuits integrated in power devices
10/25/2000EP1047128A2 Warped semiconductor device and method of manufacturing the same
10/25/2000EP1047127A2 A method of forming a multi-layered dual-polysilicon structure
10/25/2000EP1047120A1 Method of manufacturing an electrode in a semiconductor device
10/25/2000EP1047119A2 Process of crystallizing semiconductor thin film and laser irradiation system
10/25/2000EP1046917A2 Method of manufacturing an external force detection sensor
10/25/2000EP1046195A1 Thin film transistors
10/25/2000EP1046194A1 Bi-directional semiconductor switch, and switch circuit for battery-powered equipment
10/25/2000EP1046191A1 Manufacture of electronic devices comprising thin-film circuit elements
10/25/2000EP1046045A2 Method for detecting a current of spin polarized electrons in a solid body
10/25/2000EP0846340B1 Switched magnetic field sensitive field effect transistor device
10/25/2000CN1271464A Electrode means, with or without functional elements and an electrode device including polymer material and an electrode device formed of saidmeans
10/25/2000CN1271181A Semicondutor device
10/24/2000US6137728 Nonvolatile reprogrammable interconnect cell with programmable buried source/drain in sense transistor
10/24/2000US6137724 Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages
10/24/2000US6137723 Memory device having erasable Frohmann-Bentchkowsky EPROM cells that use a well-to-floating gate coupled voltage during erasure
10/24/2000US6137722 Memory array having Frohmann-Bentchkowsky EPROM cells with a reduced number of access transistors
10/24/2000US6137721 Memory device having erasable frohmann-bentchkowsky EPROM cells that use a plate-to-floating gate coupled voltage during erasure
10/24/2000US6137718 Method for operating a non-volatile memory cell arrangement
10/24/2000US6137551 Liquid crystal display, thin film transistor array, and method of fabricating same with storage capacitor providing high aspect ratio
10/24/2000US6137177 CMOS semiconductor device
10/24/2000US6137176 Semiconductor device and method of fabricating the same
10/24/2000US6137175 Semiconductor device with multi-layer wiring
10/24/2000US6137154 Bipolar transistor with increased early voltage
10/24/2000US6137153 Floating gate capacitor for use in voltage regulators
10/24/2000US6137150 Semiconductor physical-quantity sensor having a locos oxide film, for sensing a physical quantity such as acceleration, yaw rate, or the like
10/24/2000US6137149 Semiconductor device having raised source-drains and method of fabricating the same
10/24/2000US6137148 NMOS transistor
10/24/2000US6137147 Bipolar transistor and semiconductor integrated circuit device
10/24/2000US6137141 MOS device and fabrication method
10/24/2000US6137140 Integrated SCR-LDMOS power device
10/24/2000US6137139 Low voltage dual-well MOS device having high ruggedness, low on-resistance, and improved body diode reverse recovery
10/24/2000US6137138 MOSFET power transistor having offset gate and drain pads to reduce capacitance
10/24/2000US6137137 CMOS semiconductor device comprising graded N-LDD junctions with increased HCI lifetime
10/24/2000US6137136 Power semiconductor device
10/24/2000US6137135 Semiconductor device and method of fabricating the same
10/24/2000US6137134 Semiconductor memory device
10/24/2000US6137128 Self-isolated and self-aligned 4F-square vertical fet-trench dram cells
10/24/2000US6137126 Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer
10/24/2000US6137124 Integrated vertical semiconductor component
10/24/2000US6137122 Latch-up controllable insulated gate bipolar transistor
10/24/2000US6136728 Annealing the dielectric layer in a water vapor atmosphere to improve the electrical properties
10/24/2000US6136727 Preheating a silicon carbide substrate in an atmosphere comprising hydrogen, then oxidation to form silicon dioxide dielectric layer
10/24/2000US6136717 Method for producing a via hole to a doped region
10/24/2000US6136705 Depositing a silicon layer above the silicon substrate, covering a cobalt layer and then a titanium capping layer, reacting cobalt from the cobalt layer with silicon from silicon layer and from silicon substrate
10/24/2000US6136702 Thin film transistors
10/24/2000US6136701 Contact structure for semiconductor device and the manufacturing method thereof
10/24/2000US6136699 Heating to change the formed refractory metal silicide layer from a first phase structure into a second phase structure
10/24/2000US6136696 Method of forming a semiconductor device with a conductor plug including five dielectric layers, the fourth dielectric layer forming sidewall spacers
10/24/2000US6136692 Reducing contact resistance between the titanium nitride plug and the polysilicon electrode
10/24/2000US6136678 Method of processing a conductive layer and forming a semiconductor device
10/24/2000US6136675 Method for forming gate terminal
10/24/2000US6136674 Mosfet with gate plug using differential oxide growth
10/24/2000US6136658 Method of fabricating a semiconductor device including a contact hole between gate electrode structures
10/24/2000US6136657 Method for fabricating a semiconductor device having different gate oxide layers
10/24/2000US6136656 Method to create a depleted poly MOSFET
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