Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
11/2000
11/15/2000EP1052690A2 Process or forming MOS-gated devices having self-aligned trenches
11/15/2000EP1052685A2 Integrated circuit device having a fluorine implanted oxide layer
11/15/2000EP1051762A1 X-y addressable electric microswitch arrays and sensor matrices employing them
11/15/2000EP1051757A1 Lateral thin-film silicon-on-insulator (soi) device having multiple zones in the drift region
11/15/2000EP1051756A1 Mos field effect transistor with an auxiliary electrode
11/15/2000EP1051755A2 A transistor of sic
11/15/2000EP1051754A1 A field-effect transistor
11/15/2000EP1051753A1 Insulated gate bipolar transistor for zero-voltage switching
11/15/2000EP1051745A1 A method for generating electrical conducting or semiconducting structures in two or three dimensions, a method for erasing the same structures and an electric field generator/modulator for use with the method for generating
11/15/2000EP1051744A1 Method of forming a semiconductor device
11/15/2000EP1051743A1 Method of rapid thermal processing (rtp) of ion implanted silicon
11/15/2000EP1051741A1 A method for generation of electrical conducting or semiconducting structures in three dimensions and methods for erasure of the same structures
11/15/2000EP1051711A1 Semiconductor device comprising a non-volatile memory which is erasable by means of uv irradiation
11/15/2000EP0948812A4 Surface connectable semiconductor bridge elements, devices and methods
11/15/2000CN1273696A Ferroelectric memory and method of producing the same
11/15/2000CN1273436A Method for manufacturing thin film transistor and thin film transistor
11/15/2000CN1058585C Semiconductor device
11/15/2000CN1058584C Semiconductor device and fabrication method of the same
11/15/2000CN1058583C Semconductor and process for fabricating the same
11/14/2000US6147667 Semiconductor device
11/14/2000US6147388 Polycide gate structure with intermediate barrier
11/14/2000US6147386 Semiconductor device and method of producing the same
11/14/2000US6147384 Method for forming planar field effect transistors with source and drain an insulator and device constructed therefrom
11/14/2000US6147383 LDD buried channel field effect semiconductor device and manufacturing method
11/14/2000US6147382 Semiconductor switching device with segmented sources
11/14/2000US6147381 Field effect-controllable semiconductor component
11/14/2000US6147380 Floating gate non-volatile memory cell with low erasing voltage and having different potential barriers
11/14/2000US6147379 Semiconductor device and method for fabricating the same
11/14/2000US6147378 Fully recessed semiconductor device and method for low power applications with single wrap around buried drain region
11/14/2000US6147377 Fully recessed semiconductor device
11/14/2000US6147375 Active matrix display device
11/14/2000US6147374 Resin-encapsulated semiconductor apparatus
11/14/2000US6147371 Bipolar transistor and manufacturing method for same
11/14/2000US6147370 Field effect transistor with first and second drain electrodes
11/14/2000US6147369 SCR and current divider structure of electrostatic discharge protective circuit
11/14/2000US6147368 Voltage-driven power semiconductor device
11/14/2000US6147366 On chip CMOS optical element
11/14/2000US6147362 High performance display pixel for electronics displays
11/14/2000US6147359 Method of making silicon quantum wires
11/14/2000US6147014 Reacting an ammonia compound with a silane compound, wherein at least one of said compounds contains deuterium, so as to form a silicon nitride spacer containing deuterium.
11/14/2000US6147008 Creation of multiple gate oxide with high thickness ratio in flash memory process
11/14/2000US6147001 Method of manufacturing semiconductor integrated circuit device
11/14/2000US6146976 Method for producing bridged doped zones
11/14/2000US6146956 PNP lateral bipolar electronic device and corresponding manufacturing process
11/14/2000US6146954 Minimizing transistor size in integrated circuits
11/14/2000US6146953 Fabrication method for mosfet device
11/14/2000US6146952 Semiconductor device having self-aligned asymmetric source/drain regions and method of fabrication thereof
11/14/2000US6146947 Insulated gate type field effect transistor and method of manufacturing the same
11/14/2000US6146946 Method of fabricating a flash memory
11/14/2000US6146945 Method for manufacturing a semiconductor device
11/14/2000US6146934 Semiconductor device with asymmetric PMOS source/drain implant and method of manufacture thereof
11/14/2000US6146931 Method of forming a semiconductor device having a barrier layer interposed between the ohmic contact and the schottky contact
11/14/2000US6146930 Method of fabricating an active-matrix liquid crystal display
11/14/2000US6146929 Method for manufacturing semiconductor device using multiple steps continuously without exposing substrate to the atmosphere
11/14/2000US6146928 Method for manufacturing thin film transistor, liquid crystal display and electronic device both produced by the method
11/14/2000US6146927 Semiconductor device, manufacturing method therefor and liquid crystal driving apparatus comprising the semiconductor device
11/14/2000US6146926 Lateral gate, vertical drift region transistor
11/14/2000US6146904 Method of making a two transistor ferroelectric memory cell
11/14/2000US6146742 Barrier/glue layer on polysilicon layer
11/14/2000US6146543 Microbellows actuator
11/14/2000US6146505 Sputtering method for producing layered aluminium fine particles and use thereof
11/09/2000WO2000067377A2 Mask configurable smart power circuits - applications and gs-nmos devices
11/09/2000WO2000067332A1 Integrated circuit varactor having a wide capacitance range
11/09/2000WO2000067331A1 Ferroelectric field effect transistor having compositionally graded ferroelectric material and method of making the same
11/09/2000WO2000067330A1 Semiconductor device having bipolar transistors
11/09/2000WO2000067329A1 A semiconductor element
11/09/2000WO2000067327A1 Minimally-patterned semiconductor devices for display applications
11/09/2000WO2000067322A2 Self-aligned source and drain extensions fabricated in a damascene contact and gate process
11/09/2000WO2000067317A1 Semiconductor device and method of manufacturing same
11/09/2000WO2000067313A1 Double gated transistor
11/09/2000WO2000067309A1 Method of manufacturing a semiconductor device comprising a field effect transistor
11/09/2000WO2000067301A2 Method of making shallow junction semiconductor devices
11/09/2000WO2000055971A8 Methods and apparatus for bipolar elimination in silicon-on-insulator (soi) domino circuits
11/09/2000WO2000041247A3 Quantum-size electronic devices and operating conditions thereof
11/09/2000WO2000016407A3 Switching transistor with reduced switching losses
11/09/2000WO1999063580A3 Compound semiconductor structure with lattice and polarity matched heteroepitaxial layers
11/09/2000DE19920066A1 Sensor has multilayer substrate with spring element formed from semiconducting layer with arm end sections curved away then curved back towards each other, united in central curved region
11/09/2000DE19919130A1 Monolithic integrated semiconductor arrangement, e.g. for MOS transistor or bipolar transistor
11/09/2000DE19919112A1 Pressure sensor joint formation involves providing socket for connection to housing with template whose opening cross-section is smaller than chip element, retaining template when joining
11/09/2000DE10018694A1 HEMT component on InP base with Schottky barrier with variable aluminium percentage content has lower layer with first aluminium content, per layer with higher concentration region
11/09/2000CA2372101A1 Minimally-patterned semiconductor devices for display applications
11/09/2000CA2336107A1 Mask configurable smart power circuits - applications and gs-nmos devices
11/08/2000EP1050908A1 Insulating gate type bipolar semiconductor device
11/08/2000EP1050076A1 Method for producing diodes
11/08/2000EP1050071A2 Lateral thin-film silicon-on-insulator (soi) device having multiple doping profile slopes in the drift region
11/08/2000EP1050051A1 Memory device using a transistor and its fabrication method
11/08/2000EP1049956A1 Active matrix liquid crystal display devices
11/08/2000EP1049936A1 An arrangement for measuring angular velocity
11/08/2000EP1004132A4 A carbon film for field emission devices
11/08/2000CN1272695A Electrooptical device and electronic equipment
11/08/2000CN1272689A Structure of double deep oxide layer in epitaxial silicon process on insulator base
11/08/2000CN1272686A Method for forming refraction-metal-silicide layer of semi-conductor device
11/08/2000CN1272683A Semiconductor device and its manufacturing method
11/07/2000US6145107 Method for early failure recognition in power semiconductor modules
11/07/2000US6144929 Method of simulating impact ionization phenomenon in semiconductor device
11/07/2000US6144586 Methods of erasing a memory device and a method of programming a memory device for low-voltage and low-power applications
11/07/2000US6144584 Non-volatile semiconductor memory device and method of manufacturing the same
11/07/2000US6144583 Semiconductor integrated circuit device
11/07/2000US6144579 Ferroelectric memory device
11/07/2000US6144546 Capacitor having electrodes with two-dimensional conductivity
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