Patents
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
01/2001
01/11/2001CA2372707A1 Nanoscopic wire-based devices, arrays, and method of their manufacture
01/10/2001EP1067607A2 An insulated gate transistor and the method of manufacturing the same
01/10/2001EP1067597A2 Transitors with low overlap capacitance
01/10/2001EP1067596A2 Process for forming vertical semiconductor device having increased source contact area
01/10/2001EP1067593A2 Semiconductor thin film forming system
01/10/2001EP1067557A1 Flash compatible EEPROM
01/10/2001EP1066652A2 Trench-gate semiconductor devices and their manufacture
01/10/2001EP1066416A1 Passivating etchants for metallic particles
01/10/2001CN1279822A Semiconductor device and manufacture thereof
01/10/2001CN1279765A Method for detecting current of spin polarized electrons in solid body
01/10/2001CN1279517A Twin film field effect transistors and use thereof
01/10/2001CN1279516A Semiconductor device and manufacture thereof
01/10/2001CN1060590C Flash EEPROM cell and method of making the same
01/09/2001US6173235 Method of estimating lifetime of floating SOI-MOSFET
01/09/2001US6172907 Silicon-oxide-nitride-oxide-semiconductor (SONOS) type memory cell and method for retaining data in the same
01/09/2001US6172905 Method of operating a semiconductor device
01/09/2001US6172733 Liquid crystal display including conductive layer passing through multiple layers and method of manufacturing same
01/09/2001US6172729 Liquid crystal display device of delta arrangement having pixel openings with sides oblique to scan lines
01/09/2001US6172728 Reflective LCD including address lines shaped to reduce parasitic capacitance
01/09/2001US6172671 Active matrix type display device and fabrication method of the same
01/09/2001US6172420 Silicon delta-doped gallium arsenide/indium arsenide heterojunction OHMIC contact
01/09/2001US6172407 Source/drain and lightly doped drain formation at post interlevel dielectric isolation with high-K gate electrode design
01/09/2001US6172406 Breakdown drain extended NMOS
01/09/2001US6172405 Semiconductor device and production process therefore
01/09/2001US6172401 Transistor device configurations for high voltage applications and improved device performance
01/09/2001US6172400 MOS transistor with shield coplanar with gate electrode
01/09/2001US6172399 Formation of ultra-shallow semiconductor junction using microwave annealing
01/09/2001US6172398 Trenched DMOS device provided with body-dopant redistribution-compensation region for preventing punch through and adjusting threshold voltage
01/09/2001US6172397 Non-volatile semiconductor memory device
01/09/2001US6172394 Non-volatile semiconductor memory device having a floating gate with protruding conductive side-wall portions
01/09/2001US6172393 Nonvolatile memory having contactless array structure which can reserve sufficient on current, without increasing resistance, even if width of bit line is reduced and creation of hyperfine structure is tried, and method of manufacturing nonvolatile memory
01/09/2001US6172391 DRAM cell arrangement and method for the manufacture thereof
01/09/2001US6172386 A capacitor comprising a ferroelectric film formed from a group lead zirconate titanium and lead lanthanum zirconate titanate where having a relatively larger amount of titanium constituent than zinconate constituent
01/09/2001US6172384 Field effect transistor and a method for manufacturing a same
01/09/2001US6172380 Semiconductor material
01/09/2001US6172378 Integrated circuit varactor having a wide capacitance range
01/09/2001US6172370 Lateral PN arrayed digital x-ray image sensor
01/09/2001US6171981 Electrode passivation layer of semiconductor device and method for forming the same
01/09/2001US6171973 Process for etching the gate in MOS technology using a SiON-based hard mask
01/09/2001US6171961 Fabrication method of a semiconductor device
01/09/2001US6171950 Method for forming a multilevel interconnection with low contact resistance in a semiconductor device
01/09/2001US6171939 Method for forming polysilicon gate electrode
01/09/2001US6171937 Process for producing an MOS transistor
01/09/2001US6171936 Method of producing co-planar Si and Ge composite substrate
01/09/2001US6171935 Process for producing an epitaxial layer with laterally varying doping
01/09/2001US6171934 Recovery of electronic properties in process-damaged ferroelectrics by voltage-cycling
01/09/2001US6171930 Device isolation structure and device isolation method for a semiconductor power integrated circuit
01/09/2001US6171920 Method of forming heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction
01/09/2001US6171916 Semiconductor device having buried gate electrode with silicide layer and manufacture method thereof
01/09/2001US6171915 Method of fabricating a MOS-type transistor
01/09/2001US6171913 Process for manufacturing a single asymmetric pocket implant
01/09/2001US6171912 Method of manufacturing a semiconductor device comprising a field effect transistor
01/09/2001US6171910 Method for forming a semiconductor device
01/09/2001US6171908 Method of fabricating self-aligned split gate flash memory cell
01/09/2001US6171906 Method of forming sharp beak of poly to improve erase speed in split gate flash
01/09/2001US6171905 Semiconductor device and method of manufacturing the same
01/09/2001US6171900 CVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFET
01/09/2001US6171895 Fabrication of buried channel devices with shallow junction depth
01/09/2001US6171894 Method of manufacturing BICMOS integrated circuits on a conventional CMOS substrate
01/09/2001US6171891 Method of manufacture of CMOS device using additional implant regions to enhance ESD performance
01/09/2001US6171889 Semiconductor device and method of manufacturing the same
01/09/2001US6171881 Acceleration sensor and process for the production thereof
01/09/2001US6171437 Semiconductor manufacturing device
01/09/2001US6170815 Method of fabricating a thin film transistor including forming a trench and forming a gate electrode on one side of the interior of the trench
01/04/2001WO2001001496A1 Method for making a semiconductor device comprising a stack alternately consisting of silicon layers and dielectric material layers
01/04/2001WO2001001495A1 Power-switching semiconductor device
01/04/2001WO2001001494A1 Multi-directional radiation coupling in quantum-well infrared photodetectors
01/04/2001WO2001001490A1 Soi dram without floating body effect
01/04/2001WO2001001484A2 Trench mos-transistor
01/04/2001WO2001001481A1 Mos transistor and dram cell arrangement and method for the production thereof
01/04/2001WO2001001477A1 Method for lateral etching with holes for making semiconductor devices
01/04/2001WO2001001476A1 Method of producing a non-volatile semiconductor memory cell with a separate tunnel window
01/04/2001WO2001001449A2 Semiconductor device manufacturing using low energy high tilt angle ion implantation
01/04/2001WO2000059045A3 Multilayer semiconductor structure with phosphide-passivated germanium substrate
01/04/2001WO2000058999A3 Semiconductor structures having a strain compensated layer and method of fabrication
01/04/2001WO2000029824A9 Integral stress isolation apparatus and technique for semiconductor devices
01/04/2001DE19930797A1 Elektrisches Halbleiterbauelement Electric semiconductor device
01/04/2001DE19930783A1 Halbleiterbauelement Semiconductor device
01/04/2001DE19930779A1 Micromechanical component has stop spring mounted on substrate via second flexural spring device with higher flexural stiffness that first flexural spring device for seismic mass
01/04/2001DE19929235A1 Vertical DMOS transistor
01/04/2001DE19929211A1 MOS-Transistor und Verfahren zu dessen Herstellung sowie DRAM-Zellenanordnung und Verfahren zu deren Herstellung MOS transistor and method for its production as well as the DRAM cell arrangement and method for their preparation
01/04/2001DE19928564A1 Mehrkanal-MOSFET und Verfahren zu seiner Herstellung Multi-channel MOSFET and method for its preparation
01/04/2001DE10006912A1 Process for fixing a microsensor to a wafer comprises etching a holder of a base wafer, applying a sacrificial layer, forming a recess in a separate assembly wafer
01/03/2001EP1065728A2 Heterojunction bipolar transistor and method for fabricating the same
01/03/2001EP1065727A2 Edge termination for silicon power devices
01/03/2001EP1065726A1 Silicon carbide semiconductor switching device
01/03/2001EP1065710A2 Semiconductor device having a recessed gate and method of manufacturing therof
01/03/2001EP1065706A2 Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxide
01/03/2001EP1064684A1 Edge termination for a semiconductor component, schottky diode with an end termination and method for producing a schottky diode
01/03/2001CN1278967A 量子计算机 Quantum Computer
01/03/2001CN1278657A Electrostatic induction device and its manufacture
01/02/2001US6169692 Non-volatile semiconductor memory
01/02/2001US6169690 Non-volatile semiconductor memory device
01/02/2001US6169687 High density and speed magneto-electronic memory for use in computing system
01/02/2001US6169415 Characteristic evaluation apparatus for insulated gate type transistors
01/02/2001US6169324 Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same
01/02/2001US6169315 Metal oxide semiconductor field effect transistor (MOSFET) and method for making thereof
01/02/2001US6169308 Semiconductor memory device and manufacturing method thereof
01/02/2001US6169307 Nonvolatile semiconductor memory device comprising a memory transistor, a select transistor, and an intermediate diffusion layer
01/02/2001US6169306 Semiconductor devices comprised of one or more epitaxial layers