Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 23 - Details of semiconductor or other solid state devices
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
06/2009
06/25/2009WO2009077538A2 Process of assembly with buried marks
06/25/2009WO2009077268A2 Cooling body of at least one electrical component
06/25/2009WO2009076810A1 Semiconductor power module and heat radiating method thereof
06/25/2009WO2009076797A1 Power led intense light device
06/25/2009WO2009059883A4 Chip packaging
06/25/2009WO2009056387A3 Hf chip module, hf assembly and method for producing an hf assembly
06/25/2009WO2009053159A3 Fixing clamp
06/25/2009WO2009034454A3 Semiconductor device
06/25/2009WO2009013678A3 Reinforced structure for a stack of layers in a semiconductor component
06/25/2009WO2006130721A3 Printable semiconductor structures and related methods of making and assembling
06/25/2009US20090163789 Analyte Monitoring Device and Methods of Use
06/25/2009US20090163788 Analyte Monitoring Device and Methods of Use
06/25/2009US20090163781 Analyte Monitoring Device And Methods Of Use
06/25/2009US20090163161 Scalable radio receiver architecture providing three-dimensional packaging of multiple receivers
06/25/2009US20090163022 Tft array panel
06/25/2009US20090163019 Forming robust solder interconnect structures by reducing effects of seed layer underetching
06/25/2009US20090162982 Array substrate, display device having the same and method of manufacturing the same
06/25/2009US20090162974 Semiconductor package board using a metal base
06/25/2009US20090162791 Protective caps residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers; formed by depositing a first layer of aluminum-containing material over an exposed copper line by treating an oxide-free copper surface with an organoaluminum compound; integrated circuit
06/25/2009US20090161709 Multichip package, methods of manufacture thereof and articles comprising the same
06/25/2009US20090161329 Semiconductor device
06/25/2009US20090161283 Arrangements for Energy Conditioning
06/25/2009US20090160595 Compact Power Semiconductor Package and Method with Stacked Inductor and Integrated Circuit Die
06/25/2009US20090160528 Method for regulating temperature
06/25/2009US20090160482 Formation of a hybrid integrated circuit device
06/25/2009US20090160071 Die rearrangement package structure using layout process to form a compliant configuration
06/25/2009US20090160070 Metal line in a semiconductor device
06/25/2009US20090160069 Leadless alignment of a semiconductor chip
06/25/2009US20090160068 Flip-chip package and method of forming thereof
06/25/2009US20090160067 Integrated circuit package
06/25/2009US20090160066 Semiconductor element, semiconductor device, and fabrication method thereof
06/25/2009US20090160065 Reconstituted Wafer Level Stacking
06/25/2009US20090160064 Semiconductor device and method for manufacturing the device
06/25/2009US20090160063 Semiconductor Device
06/25/2009US20090160062 Semiconductor Devices and Methods of Manufacturing Thereof
06/25/2009US20090160061 Introducing a Metal Layer Between Sin and Tin to Improve CBD Contact Resistance for P-TSV
06/25/2009US20090160060 Method of manufacturing semiconductor device
06/25/2009US20090160059 Semiconductor Device Having Improved Adhesion and Reduced Blistering Between Etch Stop Layer and Dielectric Layer
06/25/2009US20090160058 Structure and process for the formation of TSVs
06/25/2009US20090160057 Semiconductor device and method of manufacturing the same
06/25/2009US20090160056 Semiconductor device and method for manufacturing the same
06/25/2009US20090160055 IC solder reflow method and materials
06/25/2009US20090160053 Method of manufacturing a semiconducotor device
06/25/2009US20090160052 Under bump metallurgy structure of semiconductor device package
06/25/2009US20090160051 Semiconductor Chip, Method of Fabricating the Same and Semiconductor Chip Stack Package
06/25/2009US20090160050 Semiconductor device manufacturing method, semiconductor device and wafer
06/25/2009US20090160049 Semiconductor device
06/25/2009US20090160048 Semiconductor Unit, and Power Conversion System and On-Vehicle Electrical System Using the Same
06/25/2009US20090160047 Downhole tool
06/25/2009US20090160046 Electronic device and method
06/25/2009US20090160045 Wafer level chip scale packaging
06/25/2009US20090160044 Semiconductor module mounting structure
06/25/2009US20090160043 Dice Rearrangement Package Structure Using Layout Process to Form a Compliant Configuration
06/25/2009US20090160042 Managed Memory Component
06/25/2009US20090160041 Substrate package structure
06/25/2009US20090160040 Low temperature ceramic microelectromechanical structures
06/25/2009US20090160039 Method and leadframe for packaging integrated circuits
06/25/2009US20090160038 Semiconductor package with leads on a chip having multi-row of bonding pads
06/25/2009US20090160037 Method of packaging integrated circuits
06/25/2009US20090160030 Methods for forming through wafer interconnects and structures resulting therefrom
06/25/2009US20090160029 Scribe Seal Structure for Improved Noise Isolation
06/25/2009US20090160028 Method for forming gaps in micromechanical device and micromechanical device
06/25/2009US20090160023 Semiconductor device and manufacturing method thereof
06/25/2009US20090160012 Semiconductor device and method for fabricating the same
06/25/2009US20090160011 Isolator and method of manufacturing the same
06/25/2009US20090160009 Semiconductor array and method for manufacturing a semiconductor array
06/25/2009US20090159883 Test pattern for semiconductor device and method for forming the test pattern
06/25/2009US20090159881 Semiconductor apparatus and method for manufacturing the same
06/25/2009US20090159561 Integrated device technology using a buried power buss for major device and circuit advantages
06/25/2009US20090159245 Heat dissipation device having a fan holder
06/25/2009DE202009004656U1 Kühler Cooler
06/25/2009DE112007002071T5 Mechanischer Aktivierungsmechanismus auf Formspeicherbasis Mechanical activation mechanism of shape memory base
06/25/2009DE10229712B4 Halbleitermodul Semiconductor module
06/25/2009DE102008062514A1 Halbleitermodul-Montagekonstruktion Semiconductor module mounting structure
06/25/2009DE102008061068A1 Elektronikbauelement Electronic component
06/25/2009DE102008059846A1 Drain-Erweiterter Feldeffekttransistor Extended drain field effect transistor
06/25/2009DE102008058895A1 Integrierte Schaltung, die einen Sensor mit Spritzgussmagnetmaterial umfasst Integrated circuit which comprises a sensor with injection molding magnetic material
06/25/2009DE102008058835A1 Elektronikbauelement Electronic component
06/25/2009DE102008057817A1 Vorrichtung und Verfahren mit einem Lötprozess Apparatus and method with a soldering process
06/25/2009DE102008011282A1 Housing arrangement for e.g. LED, in display device, has housing lower part with boundary layer that is partially formed such that mechanical holding strength is generated between filler particle and housing lower part
06/25/2009DE102007062944A1 Electronic component/circuit i.e. organic electronic component/circuit, for use in e.g. radio-frequency identification tag, has regions of carrier substrate and pattern like layer made of inorganic or organic material and spaced from layer
06/25/2009DE102007062166A1 Electronic component contacting method for electronic circuit carrier, involves changing compound in irradiation region of laser by irradiation with laser such that compound is conductive and contacting of component takes place
06/25/2009DE102007061479A1 Leuchtdiodenchip mit Überspannungsschutz LED chip with surge protection
06/25/2009DE102007061140A1 Optoelektronisches Bauelement mit Kühlelement Optoelectronic component with cooling element
06/25/2009DE102007060371A1 Rectifier chip-connection structure for use in electrode of e.g. vehicle generator, has connection-sleeve arranged at end of base part, where ends of connection-sleeve form region different from each cross sectional area of inner wall
06/25/2009DE102007058003A1 Semiconductor component for recognition of light affect in smart card, has semiconductor substrate, semiconductor structure formed in semiconductor substrate and sensor element
06/25/2009DE102006058695B4 Leistungshalbleitermodul mit stumpf gelötetem Anschlusselement Power semiconductor module with blunt soldered connection element
06/25/2009DE102005033691B4 Verfahren zur Herstellung einer Basisplatte für eine Schaltungsbaugruppe, Basisplatte für eine Schaltungsbaugruppe, und Verwendung der Basisplatte für eine Schaltungsbaugruppe A process for preparing a base plate for a circuit board, base plate for a circuit package, and use of base plate for a circuit package
06/25/2009DE102004029844B4 Halbleiterchippackung mit mehreren eingebetteten Chips Semiconductor chip package with multiple embedded chips
06/24/2009EP2073617A2 System and method for controlling the cooling of variable heat loads in heat generating devices
06/24/2009EP2073265A1 Pressure contact in an assembly comprising a power semiconductor module
06/24/2009EP2073264A1 Semiconductor device
06/24/2009EP2073263A1 Electronic device
06/24/2009EP2073262A1 Semiconductor component
06/24/2009EP2073261A1 Ceramic substrate component and electronic component using the same
06/24/2009EP2073254A1 Method of forming amorphous silica coating of low dielectric constant and amorphous silica coating of low dielectric constant obtained thereby
06/24/2009EP2072639A1 Method for adhesion promotion between the nickel and nickel alloy layer and another metal or a dielectric, such as in the manufacture of lead frames for semiconductor devices
06/24/2009EP2072458A1 Verfahren zum Bilden eines Katalysators zum Wachsen von Nanoröhrchen/Nanofasern und zum horizontalen Wachsen von Nanoröhrchen/Nanofasern
06/24/2009EP2072457A1 Method of producing an electric connection, based on nanotubes, between two opposing surfaces
06/24/2009EP1787325B1 Sub-assembly
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