Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
08/2014
08/21/2014US20140233292 3d semiconductor device
08/21/2014US20140233249 Tape package and flat panel display device including the same
08/21/2014US20140233188 Mounting structure for printed circuit board, and semiconductor device using such structure
08/21/2014US20140232017 Identification mechanism for semiconductor device die
08/21/2014US20140232016 Semiconductor device
08/21/2014US20140232015 Semiconductor Modules and Methods of Formation Thereof
08/21/2014US20140232014 Semiconductor device with buried bit line and method for fabricating the same
08/21/2014US20140232013 Backside Through Vias in a Bonded Structure
08/21/2014US20140232012 Semiconductor device
08/21/2014US20140232011 Semiconductor device and manufacturing method thereof
08/21/2014US20140232010 Integrated circuits and methods of forming the same with multi-level electrical connection
08/21/2014US20140232009 Memory circuits and routing of conductive layers thereof
08/21/2014US20140232008 Semiconductor Constructions and Methods of Forming Semiconductor Constructions
08/21/2014US20140232007 Semiconductor device and electronic apparatus
08/21/2014US20140232006 Device and Method for Manufacturing a Device
08/21/2014US20140232005 Stacked package, method of fabricating stacked package, and method of mounting stacked package fabricated by the method
08/21/2014US20140232004 Semiconductor device
08/21/2014US20140232003 Semiconductor Constructions, Semiconductor Processing Methods, Methods of Forming Contact Pads, and Methods of Forming Electrical Connections Between Metal-Containing Layers
08/21/2014US20140232002 Semiconductor device, fabrication process, and electronic device
08/21/2014US20140232001 Device Bond Pads Over Process Control Monitor Structures in a Semiconductor Die
08/21/2014US20140232000 Semiconductor arrangement and formatin thereof
08/21/2014US20140231999 Schemes for Forming Barrier Layers for Copper in Interconnect Structures
08/21/2014US20140231998 Back End of the Line (BEOL) Interconnect Scheme
08/21/2014US20140231997 Semiconductor device and method for manufacturing the same
08/21/2014US20140231996 Stacked type semiconductor device and printed circuit board
08/21/2014US20140231995 Semiconductor device, and method of manufacturing device
08/21/2014US20140231994 Apparatus for lead free solder interconnections for integrated circuits
08/21/2014US20140231993 Package-on-package structures
08/21/2014US20140231992 Millimeter wave wafer level chip scale packaging (wlcsp) device and related method
08/21/2014US20140231991 Method of Fabricating Three Dimensional Integrated Circuit
08/21/2014US20140231990 Wiring board and method for manufacturing the same
08/21/2014US20140231989 Semiconductor Device and Method of Embedding Bumps Formed on Semiconductor Die into Penetrable Adhesive Layer to Reduce Die Shifting During Encapsulation
08/21/2014US20140231988 Packaging Methods and Packaged Semiconductor Devices
08/21/2014US20140231987 Connector Structures of Integrated Circuits
08/21/2014US20140231986 Through substrate via (tsuv) structures and method of making the same
08/21/2014US20140231985 Semiconductor chip package structure
08/21/2014US20140231984 Molding Compound Structure
08/21/2014US20140231983 Film adhesive, dicing tape with film adhesive, method of manufacturing semiconductor device, and semiconductor device
08/21/2014US20140231982 Semiconductor device and manufacturing method thereof
08/21/2014US20140231981 Semiconductor device and method for manufacturing the same
08/21/2014US20140231980 Semiconductor grid array package
08/21/2014US20140231978 Semiconductor package with inner and outer leads
08/21/2014US20140231977 Semiconductor packages with low stand-off interconnections between chips
08/21/2014US20140231976 Method for producing a solder joint
08/21/2014US20140231975 Semiconductor device
08/21/2014US20140231974 Module and Method of Manufacturing a Module
08/21/2014US20140231973 Semiconductor device including electromagnetic absorption and shielding
08/21/2014US20140231972 Multi-chip package and method for manufacturing the same
08/21/2014US20140231971 Chip arrangement and a method of manufacturing a chip arrangement
08/21/2014US20140231966 Chip package and method for forming the same
08/21/2014US20140231957 Complementary back end of line (beol) capacitor
08/21/2014US20140231892 Semiconductor device and method of forming the same
08/21/2014US20140231869 Silicon Devices/Heatsinks Stack Assembly And A Method To Pull Apart A Faulty Silicon Device In Said Stack Assembly
08/21/2014US20140231862 Curable composition and method for manufacturing the same
08/21/2014US20140231861 Curable composition and method for manufacturing the same
08/21/2014US20140231815 Package for high-power semiconductor devices
08/21/2014US20140231117 Package for high frequency circuits
08/21/2014US20140230989 Method for creating a connection between metallic moulded bodies and a power semiconductor which is used to bond to thick wires or strips
08/21/2014DE112012004593T5 Leistungswandler Power converter
08/21/2014DE112011105693T5 Halbleitervorrichtung Semiconductor device
08/21/2014DE112005003614B4 Halbleiterbaugruppe für ein Schaltnetzteil und Verfahren zu dessen Montage A semiconductor assembly for a switching power supply and process for its mounting
08/21/2014DE102014102164A1 Chipanordnung und verfahren zum herstellen einer chipanordnung Chip assembly and method of manufacturing a chip arrangement
08/21/2014DE102014102087A1 Vorrichtungskontaktflecke über prozesssteuerungs-/überwachungs-strukturen in einem halbleiterchip Device pads on process control / monitoring structures in a semiconductor chip
08/21/2014DE102014102006A1 Halbleitermodule und Verfahren zu deren Bildung Semiconductor modules and methods for their formation
08/21/2014DE102014101818A1 Optische Vorrichtung als Mehrchip-Wafer-Level-Package (WLP) An optical device as a multi-chip wafer level package (WLP)
08/21/2014DE102014001217A1 Package für Hochleistungs-Halbleitervorrichtungen Package for high power semiconductor devices
08/21/2014DE102013223503A1 Halbleitervorrichtung Semiconductor device
08/21/2014DE102013202851A1 Schichtsystem zur ermittlung von eigenschaften der materialien von funktionsschichten und verfahren zu seiner herstellung Layer system for determining properties of materials of functional layers, and process for its preparation
08/21/2014DE102013108086B3 Anordnung mit einem Leistungshalbleitermodul und einer Kühleinrichtung, Kühlsystem hiermit und Verfahren zur Herstellung der Anordnung Arrangement with a power semiconductor module and a cooling device, the cooling system incorporated and methods of making the arrangement
08/21/2014DE102013101732A1 Sensorsystem Sensor system
08/21/2014DE102013002628A1 Gehäuse und Verfahren zum Verbinden zweier Gehäuseteile Housing and method for connecting two housing parts
08/21/2014DE102012009746B4 Verfahren zum Überprüfen der thermischen Kopplung zwischen einem Halbleiterbauelement und einem Kühlkörper Method for checking the thermal coupling between a semiconductor device and a heat sink
08/21/2014DE10164494B9 Verkapseltes Bauelement mit geringer Bauhöhe sowie Verfahren zur Herstellung An encapsulated device with a small overall height and methods for preparing
08/20/2014EP2768025A1 Photodiode array and method for manufacturing the same
08/20/2014EP2768020A2 Semiconductor devices and methods of fabricating the same
08/20/2014EP2768019A2 Copper bond wire and method of making the same
08/20/2014EP2768018A1 Cooler for semiconductor module, and semiconductor module
08/20/2014EP2768017A1 Cooler for semiconductor module, and semiconductor module
08/20/2014EP2768015A1 Gold/silicon eutectic chip soldering method and transistor
08/20/2014EP2767783A1 A cooling apparatus
08/20/2014EP2767782A1 Cooling apparatus
08/20/2014EP2767524A1 Silicon nitride substrate and method for manufacturing silicon nitride substrate
08/20/2014EP2766931A1 Stub minimization for wirebond assemblies without windows
08/20/2014EP2766929A1 A tamper detection arrangement
08/20/2014EP2766928A1 Stub minimization with terminal grids offset from center of package
08/20/2014EP2766927A1 Flip-chip hybridization of microelectronic components using suspended fusible resistive connection elements
08/20/2014EP2766925A1 Method for providing a connection between metal moulded bodies and a power semi-conductor which is used to join thick wires or strips
08/20/2014EP2766922A1 Power semi-conductor chip with a metal moulded body for contacting thick wires or strips, and method for the production thereof
08/20/2014EP2727898A9 Brazing filler metal, brazing filler metal paste, ceramic circuit substrate, ceramic master circuit substrate, and power semiconductor module
08/20/2014DE202014005988U1 Kühlmodul Cooling module
08/19/2014US8811526 Delta modulated low power EHF communication link
08/19/2014US8811072 Magnetoresistive random access memory (MRAM) package including a multilayer magnetic security structure
08/19/2014US8811031 Multichip module and method for manufacturing the same
08/19/2014US8811021 Electronic circuit module
08/19/2014US8811019 Electronic device, method for producing the same, and printed circuit board comprising electronic device
08/19/2014US8810352 Laminated inductor element and manufacturing method thereof
08/19/2014US8810309 Stack package and method for selecting chip in stack package
08/19/2014US8810276 Programmable structured arrays
08/19/2014US8810048 3D IC and 3D CIS structure
08/19/2014US8810047 Semiconductor device and method of manufacturing the same
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