Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 23 - Details of semiconductor or other solid state devices
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
09/2014
09/11/2014US20140252658 Semiconductor device
09/11/2014US20140252657 Package Alignment Structure and Method of Forming Same
09/11/2014US20140252655 Fan-out and heterogeneous packaging of electronic components
09/11/2014US20140252654 Semiconductor Device and Method of Forming Repassivation Layer with Reduced Opening to Contact Pad of Semiconductor Die
09/11/2014US20140252653 Layout structure of standard cell, standard cell library, and layout structure of semiconductor integrated circuit
09/11/2014US20140252652 Bonding structure of semiconductor package, method for fabricating the same, and stack-type semiconductor package
09/11/2014US20140252651 Anchor Vias for Improved Backside Metal Adhesion to Semiconductor Substrate
09/11/2014US20140252650 Semiconductor integrated circuit
09/11/2014US20140252649 Semiconductor module
09/11/2014US20140252648 Interconnect structure and method of forming the same
09/11/2014US20140252647 Warpage Reduction and Adhesion Improvement of Semiconductor Die Package
09/11/2014US20140252646 Interconnect Structure for Package-on-Package Devices
09/11/2014US20140252645 Thermal design and electrical routing for multiple stacked packages using through via insert (tvi)
09/11/2014US20140252644 Mitigating electromigration effects using parallel pillars
09/11/2014US20140252643 Semiconductor device manufacturing method and semiconductor device
09/11/2014US20140252642 Chip package and method for forming the same
09/11/2014US20140252641 Semiconductor Device and Method of Forming Ultra High Density Embedded Semiconductor Die Package
09/11/2014US20140252640 Semiconductor package having a multi-channel and a related electronic system
09/11/2014US20140252639 Integrated circuit device, method for producing mask layout, and program for producing mask layout
09/11/2014US20140252636 Interconnect structure and method of forming the same
09/11/2014US20140252635 Bonding Structures and Methods of Forming the Same
09/11/2014US20140252634 Packaging Devices and Methods for Semiconductor Devices
09/11/2014US20140252633 Method of fabricating an air gap using a damascene process and structure of same
09/11/2014US20140252632 Semiconductor devices
09/11/2014US20140252631 Semiconductor Device and Method of Forming Sacrificial Adhesive Over Contact Pads of Semiconductor Die
09/11/2014US20140252630 Self-Aligned Pitch Split For Unidirectional Metal Wiring
09/11/2014US20140252629 Self-Aligned Pitch Split for Unidirectional Metal Wiring
09/11/2014US20140252628 Interconnect structure and methods of making same
09/11/2014US20140252627 Semiconductor component comprising copper metallizations
09/11/2014US20140252626 Semiconductor package and method of fabricating the same
09/11/2014US20140252625 Method of Preventing a Pattern Collapse
09/11/2014US20140252624 Semiconductor Devices and Methods of Forming Same
09/11/2014US20140252623 Semiconductor device with advanced pad structure resistant to plasma damage and method for forming the same
09/11/2014US20140252622 Method for Forming Recess-Free Interconnect Structure
09/11/2014US20140252621 Method For Forming Interconnect Structure
09/11/2014US20140252620 Material and process for copper barrier layer
09/11/2014US20140252619 Interconnect structure that avoids insulating layer damage and methods of making the same
09/11/2014US20140252618 Method for forming interconnect structure that avoids via recess
09/11/2014US20140252617 Barrier layer conformality in copper interconnects
09/11/2014US20140252616 Electroless fill of trench in semiconductor structure
09/11/2014US20140252615 Semiconductor device using carbon nanotube, and manufacturing method thereof
09/11/2014US20140252614 Surface Treatment Method and Apparatus for Semiconductor Packaging
09/11/2014US20140252613 Semiconductor device
09/11/2014US20140252612 Wiring substrate for a semiconductor device having differential signal paths
09/11/2014US20140252611 Ball Amount Process in the Manufacturing of Integrated Circuit
09/11/2014US20140252610 Packaging Devices and Methods of Manufacture Thereof
09/11/2014US20140252609 Package-on-Package Structure and Methods for Forming the Same
09/11/2014US20140252608 Method and Apparatus for Packaging Pad Structure
09/11/2014US20140252607 Reflow film, solder bump formation method, solder joint formation method, and semiconductor device
09/11/2014US20140252606 Integrated circuit, multicore processor apparatus, and method for manufacturing integrated circuit
09/11/2014US20140252604 Stacked device and method of manufacturing the same
09/11/2014US20140252603 Semiconductor device having a conductive vias
09/11/2014US20140252602 Structure of a semiconductor chip with substrate via holes and metal bumps and a fabrication method thereof
09/11/2014US20140252601 Interconnect Structures and Methods of Forming Same
09/11/2014US20140252600 Treating Copper Surfaces for Packaging
09/11/2014US20140252599 Substrate-less interposer technology for a stacked silicon interconnect technology (ssit) product
09/11/2014US20140252598 Package Having Substrate with Embedded Metal Trace Overlapped by Landing Pad
09/11/2014US20140252597 Directly Sawing Wafers Covered with Liquid Molding Compound
09/11/2014US20140252596 Bump-on-Trace (BOT) Structures and Methods for Forming the Same
09/11/2014US20140252595 Semiconductor package including antenna layer and manufacturing method thereof
09/11/2014US20140252594 Package Structures and Methods for Forming the Same
09/11/2014US20140252593 Method and Apparatus for Connecting Packages onto Printed Circuit Boards
09/11/2014US20140252592 Pad defined contact for wafer level package
09/11/2014US20140252591 Reinforcement structure and method for controlling warpage of chip mounted on substrate
09/11/2014US20140252590 Semiconductor module cooler and semiconductor module
09/11/2014US20140252589 Charge Dissipation of Cavities
09/11/2014US20140252588 Semiconductor module
09/11/2014US20140252587 Semiconductor device, and on-board power conversion device
09/11/2014US20140252586 Semiconductor devices that include a die bonded to a substrate with a gold interface layer
09/11/2014US20140252585 Packages for Semiconductor Devices, Packaged Semiconductor Devices, and Methods of Cooling Packaged Semiconductor Devices
09/11/2014US20140252584 Method and apparatus for printing integrated circuit bond connections
09/11/2014US20140252583 Power Semiconductor Assembly and Module
09/11/2014US20140252582 Lead frame and semiconductor device
09/11/2014US20140252581 Lead frame and substrate semiconductor package
09/11/2014US20140252580 Lead frame, semiconductor package including the lead frame, and method of manufacturing the lead frame
09/11/2014US20140252579 3D-Packages and Methods for Forming the Same
09/11/2014US20140252578 Balanced stress assembly for semiconductor devices
09/11/2014US20140252577 Chip carrier structure, chip package and method of manufacturing the same
09/11/2014US20140252576 Semiconductor Device and Manufacturing Method Thereof
09/11/2014US20140252575 Lead frame for semiconductor package
09/11/2014US20140252574 Lead frame and semiconductor device
09/11/2014US20140252573 Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB
09/11/2014US20140252572 Structure and Method for 3D IC Package
09/11/2014US20140252571 Wafer-level package mitigated undercut
09/11/2014US20140252570 Lead-frame circuit package
09/11/2014US20140252569 High-frequency semiconductor package and high-frequency semiconductor device
09/11/2014US20140252568 Electromagnetic interference enclosure for radio frequency multi-chip integrated circuit packages
09/11/2014US20140252562 Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
09/11/2014US20140252561 Via-enabled package-on-package
09/11/2014US20140252559 Multiple Edge Enabled Patterning
09/11/2014US20140252558 Methods and Apparatus for Wafer Level Packaging
09/11/2014US20140252556 Single-mask spacer technique for semiconductor device features
09/11/2014US20140252541 Systems and methods for power train assemblies
09/11/2014US20140252540 Semiconductor Device and Method of Manufacturing Thereof
09/11/2014US20140252539 Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication
09/11/2014US20140252538 Electronic fuse with resistive heater
09/11/2014US20140252536 Semiconductor device and method of fabricating the same
09/11/2014US20140252496 Gate Contact Structure for FinFET
09/11/2014US20140252476 Rotated STI Diode on FinFET Technology
09/11/2014US20140252441 Semiconductor device and method of manufacturing same
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