Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 23 - Details of semiconductor or other solid state devices
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
09/2014
09/18/2014US20140264801 Semiconductor device
09/18/2014US20140264800 Power overlay structure and method of making same
09/18/2014US20140264799 Power overlay structure and method of making same
09/18/2014US20140264798 Packaged Device Comprising Non-Integer Lead Pitches and Method of Manufacturing the Same
09/18/2014US20140264797 Method of manufacturing semiconductor device
09/18/2014US20140264796 Insulated Bump Bonding
09/18/2014US20140264795 No-exposed-pad quad flat no-lead (qfn) packaging structure and method for manufacturing the same
09/18/2014US20140264794 Low cte interposer without tsv structure
09/18/2014US20140264793 Lead frame for semiconductor package with enhanced stress relief
09/18/2014US20140264792 Semiconductor packages and methods of packaging semiconductor devices
09/18/2014US20140264791 Direct external interconnect for embedded interconnect bridge package
09/18/2014US20140264790 Chip package and method for manufacturing the same
09/18/2014US20140264789 Semiconductor packages and methods of packaging semiconductor devices
09/18/2014US20140264788 High-frequency module
09/18/2014US20140264787 Differential excitation of ports to control chip-mode mediated crosstalk
09/18/2014US20140264786 Semiconductor Device Including RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction Interconnect
09/18/2014US20140264785 Chip package and method for forming the same
09/18/2014US20140264784 Metal Shielding on Die Level
09/18/2014US20140264783 Apparatus for electronic assembly with improved interconnect and associated methods
09/18/2014US20140264782 Formation of a high aspect ratio contact hole
09/18/2014US20140264779 Metal Deposition on Substrates
09/18/2014US20140264778 Precursor composition for deposition of silicon dioxide film and method for fabricating semiconductor device using the same
09/18/2014US20140264777 Nanocrystalline Diamond Three-Dimensional Films in Patterned Semiconductor Substrates
09/18/2014US20140264773 System and method for optimization of an imaged pattern of a semiconductor device
09/18/2014US20140264772 Shielding for Through-Silicon-Via
09/18/2014US20140264771 Chip package structure and manufacturing method thereof
09/18/2014US20140264770 Method of forming through substrate vias (tsvs) and singulating and releasing die having the tsvs from a mechanical support substrate
09/18/2014US20140264769 Packaging mechanisms for dies with different sizes of connectors
09/18/2014US20140264768 Die Preparation for Wafer-Level Chip Scale Package (WLCSP)
09/18/2014US20140264767 Wafer, Integrated Circuit Chip and Method for Manufacturing an Integrated Circuit Chip
09/18/2014US20140264766 System and Method for Film Stress Release
09/18/2014US20140264762 Wafer stack protection seal
09/18/2014US20140264761 Semiconductor devices and methods of making the same
09/18/2014US20140264759 Stacked wafer with coolant channels
09/18/2014US20140264756 Stacked integrated circuit
09/18/2014US20140264754 Methods of forming doped elements and related semiconductor device structures
09/18/2014US20140264751 Metal-insulator-metal (mim) capacitor
09/18/2014US20140264739 Methods of forming under device interconnect structures
09/18/2014US20140264737 Component-embedded substrate
09/18/2014US20140264736 Semiconductor Device and Method of Forming an Inductor on Polymer Matrix Composite Substrate
09/18/2014US20140264735 Inductor System and Method
09/18/2014US20140264734 Inductor With Magnetic Material
09/18/2014US20140264731 Programmable e-fuse for an integrated circuit product
09/18/2014US20140264730 Microelectronic elements with master/slave configurability
09/18/2014US20140264728 Active Tiling Placement for Improved Latch-up Immunity
09/18/2014US20140264718 Nonvolatile semiconductor memory device and method of manufacturing the same
09/18/2014US20140264709 Interconnect Structure for Connecting Dies and Methods of Forming the Same
09/18/2014US20140264693 Cover-Free Sensor Module And Method Of Making Same
09/18/2014US20140264682 Interconnect Sructure for Stacked Device and Method
09/18/2014US20140264678 Packaging for an electronic device
09/18/2014US20140264630 Integrated Structure
09/18/2014US20140264629 Local interconnect structures for high density
09/18/2014US20140264611 Semiconductor component and method of manufacture
09/18/2014US20140264605 Hybrid ETSOI Structure to Minimize Noise Coupling from TSV
09/18/2014US20140264573 Method for forming accumulation-mode field effect transistor with improved current capability
09/18/2014US20140264546 Damascene conductor for 3d array
09/18/2014US20140264481 Plug structure and process thereof
09/18/2014US20140264480 Semiconductor device and method of forming the same
09/18/2014US20140264462 Film transferable logic circuit, and methods for providing film transferable logic circuit
09/18/2014US20140264461 Metal layer enabling directed self-assembly semiconductor layout designs
09/18/2014US20140264452 Method of forming a hemt semiconductor device and structure therefor
09/18/2014US20140264426 Light emitting device mount, light emitting apparatus including the same, and leadframe
09/18/2014US20140264383 Semiconductor device and manufacturing method of the same
09/18/2014US20140264368 Semiconductor Wafer and a Process of Forming the Same
09/18/2014US20140264340 Reversible hybridization of large surface area array electronics
09/18/2014US20140264339 Heat slug having thermoelectric elements and semiconductor package including the same
09/18/2014US20140264334 Layout for reticle and wafer scanning electron microscope registration or overlay measurements
09/18/2014US20140264302 Adhesive and method of encapsulating organic electronic device using the same
09/18/2014US20140264235 Non-volatile memory device with tsi/tsv application
09/18/2014US20140263585 Method for forming interposers and stacked memory devices
09/18/2014US20140263584 Wire bonding apparatus and method
09/18/2014US20140262928 Tray for aligning semiconductor packages and test handler using the same, and method of aligning semiconductor packages and test method using the same
09/18/2014US20140262460 Connection Component with Posts and Pads
09/18/2014DE112013000419T5 System-In-Package mit eingebetteter RF-Chiplage in kernlosem Substrat System-in-Package with embedded RF chip location in coreless substrate
09/18/2014DE112012003759T5 Halbleitermodul, Schaltungs-Substrat Semiconductor module circuit substrate
09/18/2014DE112011105992T5 3D-integriertes Schaltungspaket mit Through-Mold-Kopplungsstrukturen der ersten Ebene 3D integrated circuit package with Through-Mold interconnects the first level
09/18/2014DE112011105751T5 Antifuse-Element unter Verwendung von nicht-planarer Topologie Antifuse element using non-planar topology
09/18/2014DE102014204600A1 Wafer, integrierter schaltungschip und verfahren zur herstellung eines integrierten schaltungschips Wafer, integrated circuit chip and method for producing an integrated circuit chip
09/18/2014DE102014204494A1 ESD-Schutzschaltung ESD protection circuit
09/18/2014DE102014202116A1 Metallschicht ermöglichende Halbleiterlayout-Designs mit gerichteter Selbstanordnung Metal layer enabling semiconductor layout designs with directed self-assembly
09/18/2014DE102014103529A1 Chipanordnung, waferanordnung und verfahren zu deren herstellung Chip arrangement wafer assembly and process for their preparation
09/18/2014DE102014103448A1 Metallabscheidung auf Substraten Metal deposition on substrates
09/18/2014DE102014103432A1 Halbleitergehäuse mit oberseitiger Isolierschicht Semiconductor package with upper insulating layer
09/18/2014DE102014103403A1 Chipbaugruppe und verfahren zum herstellen derselben Chip module and method of manufacturing the same
09/18/2014DE102014103344A1 Halbleiterchipkonfiguration mit Koppler Semiconductor chip configuration with coupler
09/18/2014DE102014103325A1 Leistungsschaltmodul mit verringerter Oszillation und Verfahren zur Herstellung einer Leistungsschaltmodulschaltung Power switching module with a reduced oscillation and method for manufacturing a power switching circuit module
09/18/2014DE102014103295A1 Chipanordnung und verfahren zur herstellung einer chipanordnung Chip assembly and method for manufacturing a chip arrangement
09/18/2014DE102014103293A1 Halbleitervorrichtung und Herstellungsverfahren dafür A semiconductor device and manufacturing method thereof
09/18/2014DE102014103275A1 Chipbaugruppe mit isoliertem Stift, isolierter Kontaktstelle oder isoliertem Chipträger und Verfahren zu ihrer Herstellung Chip package with insulated pin, isolated or insulated pad chip carrier and process for their preparation
09/18/2014DE102014103264A1 Integrierte Schaltungsstruktur und Verfahren zum Schutz gegen Beschädigungen des Gatedielektrikums Integrated circuit structure and procedures to protect against damage of the gate dielectric
09/18/2014DE102014103215A1 Verpackte Vorrichtung mit nicht ganzzahligen Anschlussrastern und Verfahren zu deren Herstellung Packaged device with non-integer connection grids and processes for their preparation
09/18/2014DE102014103186A1 Halbleitervorrichtung und Halbleiterpackage Semiconductor device and semiconductor package
09/18/2014DE102014103124A1 Härtende Harzzusammensetzung, Dichtungsmaterial und elektronische Vorrichtung, die das Dichtungsmaterial verwendet Curable resin composition, sealing material and electronic apparatus using the sealing material
09/18/2014DE102014004235A1 Feldeffekttransistor Field-effect transistor
09/18/2014DE102014003655A1 Trimmbare passive Komponenten auf dem Chip zur Herstellung großer Stückzahlen Trimmable passive components on the chip for high-volume production
09/18/2014DE102013204706A1 Widerstandsbelag für ein Gleichstromisoliersystem Resistance coating for a Gleichstromisoliersystem
09/18/2014DE102013204467A1 Anordnung zum Testen einer Einrichtung zum Schutz eines elektronischen Bauelements gegen Überhitzung und zugehöriges Verfahren An arrangement for testing a device for protecting an electronic device against overheating and related method
09/18/2014DE102013204337A1 Trägerbauteil mit einem Halbleiter-Substrat für elektronische Bauelemente und Verfahren zu dessen Herstellung Carrier component with a semiconductor substrate for electronic components and process for its preparation
09/18/2014DE102013204296A1 Flüssige vernetzbare Metall-Siliconharz-Zusammensetzungen Liquid metal-crosslinkable silicone resin compositions
09/18/2014DE102013204234A1 Sensor und Verfahren zum Herstellen einer Lötverbindung zwischen einem Sensor und einer Leiterplatte Sensor and method for forming a solder connection between a sensor and a printed circuit board
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