Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 23 - Details of semiconductor or other solid state devices
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
09/2014
09/18/2014US20140264914 Chip package-in-package and method thereof
09/18/2014US20140264913 Semiconductor Device
09/18/2014US20140264912 Semiconductor Device
09/18/2014US20140264911 Through silicon vias
09/18/2014US20140264910 Interconnect structures with polymer core
09/18/2014US20140264908 Dual damascene gap filling process
09/18/2014US20140264907 Stubby pads for channel cross-talk reduction
09/18/2014US20140264906 Systems and methods for high-speed, low-profile memory packages and pinout designs
09/18/2014US20140264905 Semiconductor Device and Method of Forming WLCSP with Semiconductor Die Embedded within Interconnect Structure
09/18/2014US20140264904 Unified pcb design for ssd applications, various density configurations, and direct nand access
09/18/2014US20140264903 Interconnect structure and method of forming the same
09/18/2014US20140264902 Novel Patterning Approach for Improved Via Landing Profile
09/18/2014US20140264901 Semiconductor device and layout design system
09/18/2014US20140264899 Pattern Modification with a Preferred Position Function
09/18/2014US20140264898 3-D IC Device with Enhanced Contact Area
09/18/2014US20140264897 Damascene conductor for a 3d device
09/18/2014US20140264896 Structure and Method for a Low-K Dielectric with Pillar-Type Air-Gaps
09/18/2014US20140264895 Semiconductor Devices and Methods of Manufacture Thereof
09/18/2014US20140264893 Pitch-halving integrated circuit process and integrated circuit structure made thereby
09/18/2014US20140264892 Semiconductor device with dummy lines
09/18/2014US20140264890 Novel pillar structure for use in packaging integrated circuit products and methods of making such a pillar structure
09/18/2014US20140264889 Semiconductor device channels
09/18/2014US20140264888 Semiconductor package structure and method of manufacturing the same
09/18/2014US20140264887 Oriented crystal nanowire interconnects
09/18/2014US20140264886 Forming Fence Conductors Using Spacer Pattern Transfer
09/18/2014US20140264885 Apparatus and Method for Wafer Separation
09/18/2014US20140264884 WLCSP Interconnect Apparatus and Method
09/18/2014US20140264883 Interconnect Structure and Method of Forming Same
09/18/2014US20140264882 Forming Fence Conductors Using Spacer Etched Trenches
09/18/2014US20140264881 Methods and structures to facilitate through-silicon vias
09/18/2014US20140264880 Interconnect structure and method of forming the same
09/18/2014US20140264878 Copper interconnect structures and methods of making same
09/18/2014US20140264877 Metallization systems of semiconductor devices comprising a copper/silicon compound as a barrier material
09/18/2014US20140264876 Multi-layer barrier layer stacks for interconnect structures
09/18/2014US20140264875 Semiconductor device and manufacturing method thereof
09/18/2014US20140264874 Electro-Migration Barrier for Cu Interconnect
09/18/2014US20140264872 Metal Capping Layer for Interconnect Applications
09/18/2014US20140264871 Method to Increase Interconnect Reliability
09/18/2014US20140264870 Method of back-end-of-line (beol) fabrication, and devices formed by the method
09/18/2014US20140264869 Semiconductor Device
09/18/2014US20140264868 Wafer-level die attach metallization
09/18/2014US20140264867 Method of forming hybrid diffusion barrier layer and semiconductor device thereof
09/18/2014US20140264866 Chemical direct pattern plating interconnect metallization and metal structure produced by the same
09/18/2014US20140264865 Semiconductor device and manufacturing method thereof
09/18/2014US20140264864 Integrated circuit structure and formation
09/18/2014US20140264863 Conductive Line System and Process
09/18/2014US20140264859 Packaging Devices and Methods of Manufacture Thereof
09/18/2014US20140264858 Package-on-Package Joint Structure with Molding Open Bumps
09/18/2014US20140264857 Package-on-Package with Via on Pad Connections
09/18/2014US20140264856 Package-on-Package Structures and Methods for Forming the Same
09/18/2014US20140264855 Semiconductor composite layer structure and semiconductor packaging structure having the same thereof
09/18/2014US20140264854 Multi-chip module with self-populating positive features
09/18/2014US20140264853 Adhesion between Post-Passivation Interconnect Structure and Polymer
09/18/2014US20140264852 Method for forming bumps in substrates with through vias
09/18/2014US20140264851 Semiconductor Device and Method of Forming UBM Structure on Back Surface of TSV Semiconductor Wafer
09/18/2014US20140264850 Semiconductor Device and Method of Forming a Dual UBM Structure for Lead Free Bump Connections
09/18/2014US20140264849 Package-on-Package Structure
09/18/2014US20140264848 Semiconductor package and method for fabricating the same
09/18/2014US20140264847 Semiconductor device
09/18/2014US20140264846 Packaging Devices, Methods of Manufacture Thereof, and Packaging Methods
09/18/2014US20140264845 Wafer-level package device having high-standoff peripheral solder bumps
09/18/2014US20140264844 Semiconductor device having a die and through substrate-via
09/18/2014US20140264843 Integrated Circuit Structure Having Dies with Connectors
09/18/2014US20140264842 Package-on-Package Structure and Method of Forming Same
09/18/2014US20140264841 Surface Treatment in Electroless Process for Adhesion Enhancement
09/18/2014US20140264840 Package-on-Package Structure
09/18/2014US20140264839 Packaged Semiconductor Devices, Methods of Packaging Semiconductor Devices, and PoP Devices
09/18/2014US20140264838 Method and Apparatus for a Conductive Bump Structure
09/18/2014US20140264837 Semiconductor device with post-passivation interconnect structure and method of forming the same
09/18/2014US20140264836 System-in-package with interposer pitch adapter
09/18/2014US20140264835 Semiconductor packages and methods of packaging semiconductor devices
09/18/2014US20140264834 Low Cost and Ultra-Thin Chip on Wafer on Substrate (CoWoS) Formation
09/18/2014US20140264833 Semiconductor package and method for fabricating the same
09/18/2014US20140264832 Chip arrangements
09/18/2014US20140264831 Chip arrangement and a method for manufacturing a chip arrangement
09/18/2014US20140264830 Bumpless build-up layer (bbul) semiconductor package with ultra-thin dielectric layer
09/18/2014US20140264829 Electronic assembly with copper pillar attach substrate
09/18/2014US20140264828 Method and Apparatus for a Conductive Pillar Structure
09/18/2014US20140264827 Methods of forming wafer level underfill materials and structures formed thereby
09/18/2014US20140264826 Semiconductor device and semiconductor device fabrication method
09/18/2014US20140264824 Methods and Apparatus of Packaging Semiconductor Devices
09/18/2014US20140264822 Thermosetting resin compositions with low coefficient of thermal expansion
09/18/2014US20140264821 Molded heat spreaders
09/18/2014US20140264820 Paste thermal interface materials
09/18/2014US20140264819 Semiconductor device and manufacturing method thereof
09/18/2014US20140264818 Polymer thermal interface material having enhanced thermal conductivity
09/18/2014US20140264817 Semiconductor Device and Method of Using Partial Wafer Singulation for Improved Wafer Level Embedded System in Package
09/18/2014US20140264816 Semiconductor package structure
09/18/2014US20140264815 Semiconductor Device Package and Method
09/18/2014US20140264814 Semiconductor chip, method for manufacturing a semiconductor chip, device and method for manufacturing a device
09/18/2014US20140264813 Semiconductor Device Package and Method
09/18/2014US20140264810 Packages with Molding Material Forming Steps
09/18/2014US20140264809 Backplate interconnect with integrated passives
09/18/2014US20140264808 Chip arrangements, chip packages, and a method for manufacturing a chip arrangement
09/18/2014US20140264807 Semiconductor device
09/18/2014US20140264806 Semiconductor devices and methods of making the same
09/18/2014US20140264805 Semiconductor Package And Fabrication Method Thereof
09/18/2014US20140264804 Stack die package
09/18/2014US20140264803 Package device including an opening in a flexible substrate and methods of forming the same
09/18/2014US20140264802 Semiconductor Device with Thick Bottom Metal and Preparation Method Thereof
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