Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
04/2010
04/20/2010US7701055 Light emitter assembly
04/20/2010US7701054 Power semiconductor module and method for its manufacture
04/20/2010US7701053 Electronic component and method for producing the same
04/20/2010US7701052 Power core devices
04/20/2010US7701051 Power semiconductor module
04/20/2010US7701050 Side-view optical diode package and fabricating process thereof
04/20/2010US7701049 Integrated circuit packaging system for fine pitch substrates
04/20/2010US7701048 Power module for low thermal resistance and method of fabricating the same
04/20/2010US7701047 Integrated-circuit chip with offset external pads and method for fabricating such a chip
04/20/2010US7701046 Stacked type chip package structure
04/20/2010US7701045 Point-to-point connection topology for stacked devices
04/20/2010US7701044 Chip package for image sensor and method of manufacturing the same
04/20/2010US7701043 Lead frame
04/20/2010US7701042 Integrated circuit package system for chip on lead
04/20/2010US7701041 Chip-packaging with bonding options having a plurality of package substrates
04/20/2010US7701040 Semiconductor package and method of reducing electromagnetic interference between devices
04/20/2010US7701039 Semiconductor devices and in-process semiconductor devices having conductor filled vias
04/20/2010US7701036 Inductor with plural coil layers
04/20/2010US7701035 Laser fuse structures for high power applications
04/20/2010US7701033 Isolation structures for integrated circuits
04/20/2010US7701021 Functional device, semiconductor device, and electronic device
04/20/2010US7701015 Bipolar and CMOS integration with reduced contact height
04/20/2010US7701012 Complementary zener triggered bipolar ESD protection
04/20/2010US7700999 SRAM device
04/20/2010US7700986 Chip package carrier and fabrication method thereof
04/20/2010US7700977 Integrated circuit with a subsurface diode
04/20/2010US7700958 Light emitting device having pixel portion surrounded by first sealing material and covered with second sealing material
04/20/2010US7700957 Process for making contact with and housing integrated circuits
04/20/2010US7700956 Sensor component and panel used for the production thereof
04/20/2010US7700952 Contact pad for thin film transistor substrate and liquid crystal display
04/20/2010US7700948 Thin film transistor array panel with common bars of different widths
04/20/2010US7700945 On-chip storage of hardware events for debugging
04/20/2010US7700944 Semiconductor wafer, semiconductor chip, and semiconductor chip inspection method
04/20/2010US7700487 Semiconductor device and manufacturing method of semiconductor device
04/20/2010US7700475 Pillar structure on bump pad
04/20/2010US7700407 Method of forming a bump-on-lead flip chip interconnection having higher escape routing density
04/20/2010US7700404 Large die package structures and fabrication method therefor
04/20/2010US7700397 Process for packaging components, and packaged components
04/20/2010US7700383 Manufacturing method for semiconductor device and determination method for position of semiconductor element
04/20/2010US7700381 Semiconductor wafer with ID mark, equipment for and method of manufacturing semiconductor device from them
04/20/2010US7699210 Soldering an electronics package to a motherboard
04/20/2010US7698815 Method for forming a heat dissipation device
04/20/2010US7698800 Element arrangement method
04/15/2010WO2010042573A1 Substrate for lighting device and production thereof
04/15/2010WO2010041651A1 Semiconductor device
04/15/2010WO2010041630A1 Semiconductor device and method for manufacturing same
04/15/2010WO2010041529A1 Method of manufacturing heat transfer plate
04/15/2010WO2010041510A1 Flexible conductor-clad laminate, flexible printed wiring board for cof, and methods for manufacturing same
04/15/2010WO2010041376A1 Interposer substrate and semiconductor device
04/15/2010WO2010041365A1 Semiconductor device
04/15/2010WO2010041363A1 Semiconductor device and method for manufacturing semiconductor device
04/15/2010WO2010041356A1 Manufacturing method of electronic parts modules
04/15/2010WO2010041175A1 Power semiconductor device adaptive cooling assembly
04/15/2010WO2010041165A1 Method of plating through wafer vias in a wafer for 3d packaging
04/15/2010WO2010040398A1 Chip interconnection
04/15/2010WO2010011503A3 Memory system and method using stacked memory device dice, and system using the memory system
04/15/2010WO2009148722A3 Adhesive encapsulating composition and electronic devices made therewith
04/15/2010WO2008154526A4 Method to make low resistance contact
04/15/2010WO2008063138A3 An improved ball mounting apparatus and method
04/15/2010US20100093947 Adamantane derivative, method for producing the same, resin composition containing the adamantane derivative and use thereof
04/15/2010US20100093158 Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors and fabricating such devices
04/15/2010US20100091633 Method for manufacturing semiconductor device, semiconductor device and optical pickup module
04/15/2010US20100091630 Method for manufacturing semiconductor device, optical pickup module and semiconductor device
04/15/2010US20100091463 Cooling body
04/15/2010US20100090751 Electrical Fuse Structure and Method
04/15/2010US20100090714 Sensing circuit for devices with protective coating
04/15/2010US20100090353 Pad structure of semiconductor integrated circuit apparatus
04/15/2010US20100090352 Flip-chip substrate and method of manufacturing the same
04/15/2010US20100090351 Electro component package
04/15/2010US20100090350 Multi-chip package system incorporating an internal stacking module with support protrusions
04/15/2010US20100090349 Methods of forming fine patterns in the fabrication of semiconductor devices
04/15/2010US20100090348 Single-Sided Trench Contact Window
04/15/2010US20100090347 Apparatus and method for contact formation in semiconductor devices
04/15/2010US20100090346 Integration of self-aligned trenches in-between metal lines
04/15/2010US20100090345 Direct growth of metal nanoplates on semiconductor substrates
04/15/2010US20100090344 Semiconductor device
04/15/2010US20100090343 Interconnect Structure for Semiconductor Devices
04/15/2010US20100090342 Metal Line Formation Through Silicon/Germanium Soaking
04/15/2010US20100090341 Nano-patterned active layers formed by nano-imprint lithography
04/15/2010US20100090340 Drawn Dummy FeCAP, Via and Metal Structures
04/15/2010US20100090339 Structures and Methods for Wafer Packages, and Probes
04/15/2010US20100090338 Microelectronic devices including multiple through-silicon via structures on a conductive pad and methods of fabricating the same
04/15/2010US20100090337 System and method for multi-layer global bitlines
04/15/2010US20100090336 Semiconductor element cooling structure
04/15/2010US20100090335 Semiconductor package for discharging heat and method for fabricating the same
04/15/2010US20100090334 Electronic Part Manufacturing Method
04/15/2010US20100090333 Semiconductor device, manufacturing method thereof, and manufacturing method of semiconductor module
04/15/2010US20100090332 Ceramic chip assembly
04/15/2010US20100090331 Semiconductor die package including multiple dies and a common node structure
04/15/2010US20100090330 Semiconductor device and method of manufacturing the same
04/15/2010US20100090329 High-power device having thermocouple embedded therein and method for manufacturing the same
04/15/2010US20100090328 Power semiconductor module with a hermetically tight circuit arrangement and method for producing such a module
04/15/2010US20100090327 Semiconductor device with improved resin configuration
04/15/2010US20100090324 Semiconductor package having solder ball which has double connection structure
04/15/2010US20100090323 Composite type semiconductor device spacer sheet, semiconductor package using the same, composite type semiconductor device manufacturing method, and composite type semiconductor device
04/15/2010US20100090322 Packaging Systems and Methods
04/15/2010US20100090321 High-k etch stop layer of reduced thickness for patterning a dielectric material during fabrication of transistors
04/15/2010US20100090319 Bond Pad Connection to Redistribution Lines Having Tapered Profiles
04/15/2010US20100090318 Backside Connection to TSVs Having Redistribution Lines
04/15/2010US20100090317 Interconnect Structures and Methods