Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
12/2010
12/16/2010WO2010143273A1 Semiconductor device
12/16/2010WO2010143245A1 Wiring forming method and semiconductor device
12/16/2010WO2010143233A1 Ic socket for batch processing system using ic tray
12/16/2010WO2010143132A1 Crimp bump interconnection
12/16/2010WO2010143081A1 Enhanced integrated circuit package
12/16/2010WO2010143080A1 Integrated circuit package having a castellated heatspreader
12/16/2010WO2010142804A1 Method for positioning chips during the production of a reconstituted wafer
12/16/2010WO2010142793A1 Microelectronic device provided with an array of elements made from a conductive polymer with a positive temperature coefficient
12/16/2010WO2010142475A1 Method for producing electronic components
12/16/2010WO2010142333A1 Cooling arrangement and method for assembling the cooling arrangement
12/16/2010WO2010142243A1 Optical module for transmitting and/or receiving optical signal, pedestal of photoelectric component, photoelectric component
12/16/2010WO2010081475A3 Evaporator, cooling device and method of manufacture
12/16/2010WO2010065457A3 Method of providing a semiconductor device with a dielectric layer and semiconductor device thereof
12/16/2010WO2010062946A3 Antenna integrated in a semiconductor chip
12/16/2010US20100317188 Fluorine doped carbon films produced by modification by radicals
12/16/2010US20100315938 Low distortion package for a mems device including memory
12/16/2010US20100315183 Mounting structure of electronic circuit unit
12/16/2010US20100314783 Photosensitive adhesive composition, and obtained using the same, adhesive film, adhesive sheet, semiconductor wafer with adhesive layer, semiconductor device and electronic part
12/16/2010US20100314782 Dicing tape-integrated film for semiconductor back surface
12/16/2010US20100314781 Dicing tape-integrated film for semiconductor back surface
12/16/2010US20100314780 Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Non-Linear Portions of Conductive Layers
12/16/2010US20100314779 Semiconductor device that suppresses malfunctions due to noise generated in internal circuit
12/16/2010US20100314778 Semiconductor device and method for producing the same
12/16/2010US20100314777 Semiconductor device and method for manufacturing same
12/16/2010US20100314776 Connection pad structure for an image sensor on a thinned substrate
12/16/2010US20100314775 Explosion-proof module structure for power components, particularly power semiconductor components, and production thereof
12/16/2010US20100314774 Reliable interconnects
12/16/2010US20100314773 Semiconductor device
12/16/2010US20100314772 Stacked Layer Type Semiconductor Device and Semiconductor System Including the Same
12/16/2010US20100314771 Semiconductor device including an improved lithographic margin
12/16/2010US20100314770 Mounting Substrate and Electronic Apparatus
12/16/2010US20100314769 For reducing electromigration effect in an integrated circuit
12/16/2010US20100314768 Interconnect structure fabricated without dry plasma etch processing
12/16/2010US20100314767 Self-aligned dual damascene beol structures with patternable low- k material and methods of forming same
12/16/2010US20100314766 Ulsi micro-interconnect member having ruthenium electroplating layer on barrier layer
12/16/2010US20100314765 Interconnection structure of semiconductor integrated circuit and method for making the same
12/16/2010US20100314764 Hybrid metallic wire and methods of fabricating same
12/16/2010US20100314763 Integrated circuit system employing low-k dielectrics and method of manufacture thereof
12/16/2010US20100314762 Semiconductor Substrate with Through-Contact and Method for Production Thereof
12/16/2010US20100314761 Semiconductor device with reduced cross talk
12/16/2010US20100314760 Semiconductor package and method of fabricating the same
12/16/2010US20100314759 Semiconductor chip passivation structures and methods of making the same
12/16/2010US20100314758 Through-silicon via structure and a process for forming the same
12/16/2010US20100314757 Semiconductor device and method of manufacturing the same
12/16/2010US20100314756 Interconnect Structures Having Lead-Free Solder Bumps
12/16/2010US20100314755 Printed circuit board, semiconductor device comprising the same, and method of manufacturing the same
12/16/2010US20100314754 Method of forming wire bonds in semiconductor devices
12/16/2010US20100314753 System and method for reducing process-induced charging
12/16/2010US20100314752 Forming an etched planarised photonic crystal structure
12/16/2010US20100314751 Processes and structures for IC fabrication
12/16/2010US20100314750 Integrated circuit package having security feature and method of manufacturing same
12/16/2010US20100314749 Semiconductor device having a sealing resin and method of manufacturing the same
12/16/2010US20100314748 Chip packaging method and structure thereof
12/16/2010US20100314747 Electronic device package and method of manufacture
12/16/2010US20100314746 Semiconductor package and manufacturing method thereof
12/16/2010US20100314745 Copper pillar bonding for fine pitch flip chip devices
12/16/2010US20100314744 Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof
12/16/2010US20100314743 Integrated circuit package having a castellated heatspreader
12/16/2010US20100314742 Semiconductor package
12/16/2010US20100314741 Integrated circuit package stacking system with redistribution and method of manufacture thereof
12/16/2010US20100314740 Semiconductor package, stack module, card, and electronic system
12/16/2010US20100314739 Package-on-package technology for fan-out wafer-level packaging
12/16/2010US20100314737 Intra-Die Routing Using Back Side Redistribution Layer and Associated Method
12/16/2010US20100314736 Integrated circuit packaging system with package-on-package and method of manufacture thereof
12/16/2010US20100314735 Processes and structures for IC fabrication
12/16/2010US20100314734 Processes and structures for IC fabrication
12/16/2010US20100314733 Apparatus for restricting moisture ingress
12/16/2010US20100314732 Enhanced integrated circuit package
12/16/2010US20100314731 Integrated circuit packaging system with high lead count and method of manufacture thereof
12/16/2010US20100314730 Stacked hybrid interposer through silicon via (TSV) package
12/16/2010US20100314729 Stacked Chip Package Structure with Leadframe Having Inner Leads with Transfer Pad
12/16/2010US20100314728 Ic package having an inductor etched into a leadframe thereof
12/16/2010US20100314727 Semiconductor device
12/16/2010US20100314726 Faraday cage for circuitry using substrates
12/16/2010US20100314725 Stress Balance Layer on Semiconductor Wafer Backside
12/16/2010US20100314724 Selective UV-Ozone Dry Etching of Anti-Stiction Coatings for MEMS Device Fabrication
12/16/2010US20100314721 Semiconductor Package and Method for Producing the Same
12/16/2010US20100314720 Electronic device and method for fabricating the same
12/16/2010US20100314719 Processes and structures for IC fabrication
12/16/2010US20100314718 Processes and structures for IC fabrication
12/16/2010US20100314714 Integrated circuit device
12/16/2010US20100314709 Latch-up prevention structure and method for ultra-small high voltage tolerant cell
12/16/2010US20100314698 Methods of manufacturing metal-silicide features
12/16/2010US20100314689 Local metallization and use thereof in semiconductor devices
12/16/2010US20100314676 Semiconductor device having plural dram memory cells and a logic circuit and method for manufacturing the same
12/16/2010US20100314668 Device with integrated circuit and encapsulated n/mems and method for production
12/16/2010US20100314637 Heat releasing semiconductor package, method for manufacturing the same, and display apparatus including the same
12/16/2010US20100314620 Semiconductor device
12/16/2010US20100314619 Test Structures and Methods for Semiconductor Devices
12/16/2010US20100314078 Cooler with ground heated plane and grinding method and apparatus thereof
12/16/2010US20100314072 Base plate with tailored interface
12/16/2010DE202010014116U1 Leuchtmittel mit mindestens einer Lumineszenzdiode auf einem Bauelementeträger Lamp with at least one light emitting diode devices on a carrier
12/16/2010DE202010014106U1 Wärmeverteiler mit flexibel gelagertem Wärmerohr Heat spreader with a flexible contact heat pipe
12/16/2010DE202009018077U1 Leistungselektronikanordnung Power electronics assembly
12/16/2010DE10341560B4 Leistungs-Halbleitervorrichtung Power semiconductor device
12/16/2010DE10310067B4 Halbleitervorrichtung mit hohlzylindrischer Gehäuseelektrode A semiconductor device with a hollow cylindrical housing electrode
12/16/2010DE102010017371A1 Teststrukturen und -verfahren für Halbleiterbauelemente Test structures and methods for semiconductor devices
12/16/2010DE102009024385A1 Verfahren zur Herstellung eines Leistungshalbleitermoduls und Leistungshalbleitermodul mit einer Verbindungseinrichtung Method for producing a power semiconductor module and power semiconductor module with a connecting device
12/16/2010DE102009024371A1 Verfahren zur Herstellung einer Stromrichteranordnung mit Kühleinrichtung und Stromrichteranordnung Process for the preparation of a converter arrangement with cooling device and power converter arrangement
12/16/2010DE102009024370A1 Stromrichteranordnung mit Kühleinrichtung und Herstellungsverfahren hierzu Converter arrangement with cooling device and manufacturing method therefor