Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
02/2011
02/03/2011WO2011014479A1 A coating for thermoelectric materials and a device containing the same
02/03/2011WO2011014434A2 Bond and probe pad distribution and package architecture
02/03/2011WO2011014409A1 System-in packages
02/03/2011WO2011013966A2 Method for manufacturing a heat-dissipating substrate for an led, and structure thereof
02/03/2011WO2011013923A2 Package aggregate for manufacturing semiconductor packages
02/03/2011WO2011013811A1 Semiconductor device production apparatus and semiconductor device production method
02/03/2011WO2011013776A1 Sealing glass, sealing material and sealing material paste for semiconductor devices, and semiconductor device and process for production thereof
02/03/2011WO2011013673A1 Wiring substrate and manufacturing method for wiring substrate
02/03/2011WO2011013571A1 Phenol compound and method for producing same
02/03/2011WO2011013508A1 Electronic component
02/03/2011WO2011013326A1 Liquid resin composition and semiconductor device formed using same
02/03/2011WO2011012976A1 Method and device for temperature conditioning of an element
02/03/2011WO2011011974A1 Flexible circuit module
02/03/2011WO2011011880A1 A method of manufacturing substrates having asymmetric buildup layers
02/03/2011WO2010144843A3 Intra-die routing using through-silicon via and back side redistribution layer and associated method
02/03/2011WO2010096473A3 Semiconductor chip with reinforcement layer
02/03/2011WO2010011009A9 Metal substrate for an electronic component module, module comprising same, and method for manufacturing a metal substrate for an electronic component module
02/03/2011US20110027934 Photoelectric conversion apparatus and image pickup system using photoelectric conversion apparatus
02/03/2011US20110025406 Power Semiconductor Component Including a Potential Probe
02/03/2011US20110025359 Bond and probe pad distribution
02/03/2011US20110024924 Method and structure of stacking scatterometry-based overlay or cd marks for mark footprint reduction
02/03/2011US20110024923 Wafer level hermetic bond using metal alloy with keeper layer
02/03/2011US20110024922 Semiconductor device and programming method
02/03/2011US20110024921 Contact layout structure
02/03/2011US20110024920 Component arrangement and method for producing a component arrangement
02/03/2011US20110024919 Wiring substrate for a semiconductor chip and semiconductor package having the wiring substrate
02/03/2011US20110024918 Stacked semiconductor chips
02/03/2011US20110024916 Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias
02/03/2011US20110024915 Semiconductor device
02/03/2011US20110024914 Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules
02/03/2011US20110024913 Semiconductor device
02/03/2011US20110024912 Cmos device including molecular storage elements in a via level
02/03/2011US20110024911 Semiconductor device and method for manufacturing the same
02/03/2011US20110024910 Metallurgy for copper plated wafers
02/03/2011US20110024909 Bilayer metal capping layer for interconnect applications
02/03/2011US20110024908 Low resistance high reliability contact via and metal line structure for semiconductor device
02/03/2011US20110024907 Semiconductor device and method of manufacturing the same
02/03/2011US20110024906 Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
02/03/2011US20110024905 Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
02/03/2011US20110024904 Semiconductor package, package-on-package semiconductor device, and manufacturing method thereof
02/03/2011US20110024903 Semiconductor Device and Method of Forming Wafer Level Ground Plane and Power Ring
02/03/2011US20110024902 Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
02/03/2011US20110024901 Manufacturing method of semiconductor device and semiconductor device
02/03/2011US20110024900 Semiconductor device including a stress buffer material formed above a low-k metallization system
02/03/2011US20110024899 Substrate structure for cavity package
02/03/2011US20110024898 Method of manufacturing substrates having asymmetric buildup layers
02/03/2011US20110024897 Method of assembling semiconductor devices with leds
02/03/2011US20110024896 Power semiconductor device
02/03/2011US20110024895 Semiconductor Package Thermal Performance Enhancement and Method
02/03/2011US20110024894 Chip package and manufacturing method thereof
02/03/2011US20110024893 Stacked semiconductor package and method for manufacturing the same
02/03/2011US20110024892 Thermally enhanced heat spreader for flip chip packaging
02/03/2011US20110024891 Method of reducing memory card edge roughness by edge coating
02/03/2011US20110024890 Stackable Package By Using Internal Stacking Modules
02/03/2011US20110024888 Semiconductor Device and Method of Mounting Die with TSV in Cavity of Substrate for Electrical Interconnect of FI-POP
02/03/2011US20110024887 Integrated circuit packaging system with through silicon via base and method of manufacture thereof
02/03/2011US20110024886 Semiconductor device package having features formed by stamping
02/03/2011US20110024885 Method for making semiconductor chips having coated portions
02/03/2011US20110024884 Structure of Mixed Semiconductor Encapsulation Structure with Multiple Chips and Capacitors
02/03/2011US20110024883 Semiconductor device, semiconductor module, method for manufacturing semiconductor device, and lead frame
02/03/2011US20110024882 Semiconductor device
02/03/2011US20110024881 Semiconductor device having under-filled die in a die stack
02/03/2011US20110024879 Method to reduce pre-alignment error using multi-notch pattern or in combination with flat side
02/03/2011US20110024873 Semiconductor device having a fuse region and method for forming the same
02/03/2011US20110024872 Fuse of semiconductor device and method of forming the same
02/03/2011US20110024869 Design method, design program and design support device for semiconductor integrated circuit, and semiconductor integrated circuit
02/03/2011US20110024866 CMOS IMAGE SENSOR BIG VIA BONDING PAD APPLICATION FOR AICu PROCESS
02/03/2011US20110024864 Semiconductor device and method for manufacturing the same
02/03/2011US20110024848 Methods and devices for shielding a signal line over an active region
02/03/2011US20110024806 Semiconductor devices with enclosed void cavities
02/03/2011US20110024800 Shared Resources in a Chip Multiprocessor
02/03/2011US20110024773 Light emitting diode package structure and lead frame structure thereof
02/03/2011US20110024746 Semiconductor Device with Test Pads and Pad Connection Unit
02/03/2011US20110024745 System With Semiconductor Components Having Encapsulated Through Wire Interconnects (TWI)
02/03/2011US20110024744 Connection pad structure for an electronic component
02/03/2011US20110024743 Semiconductor integrated circuit
02/03/2011US20110024164 Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
02/03/2011DE19964499B4 Ohmscher Kontakt zu Halbleitervorrichtungen und ein Verfahren zum Herstellen desselben Of the same ohmic contact to the semiconductor devices and a method for producing
02/03/2011DE102010017814A1 Elektronische Steuereinheit Electronic control unit
02/03/2011DE102010017788A1 Halbleitermodul Semiconductor module
02/03/2011DE102010017522A1 Antriebsvorrichtung und Halbleitermodul Driving device and semiconductor module
02/03/2011DE102010016274A1 Semiconductor device for electronic product, has cell contact plug, cell bit line pattern, peripheral contact plug and peripheral gate pattern having upper surfaces formed at same level
02/03/2011DE102009035819A1 Leistungshalbleitermodul mit stromsymmetrischem Lastanschlusselement Power semiconductor module with stromsymmetrischem load connection element
02/03/2011DE102009035436A1 Dreidimensionales Halbleiterbauelement mit einer Zwischenchipverbindung auf der Grundlage funktionaler Moleküle Three-dimensional semiconductor device is a two-chip interconnection on the basis of functional molecules
02/03/2011DE102009035392A1 Organisches Bauteil und Verfahren zu dessen Herstellung Organic component and method for its production
02/03/2011DE102009028037A1 Bauelement mit einer elektrischen Durchkontaktierung, Verfahren zur Herstellung eines Bauelementes und Bauelementsystem Device with an electrical through-contact, methods for producing a component and device system
02/03/2011DE102007052593B4 Kühlanordnung und elektrisches Gerät mit einer solchen Cooling assembly and electrical apparatus with such a
02/03/2011DE102006023168B4 Herstellungsverfahren für eine elektronische Schaltung Manufacturing method for an electronic circuit
02/03/2011CA2769176A1 Liquid resin composition and semiconductor device using the same
02/02/2011EP2280458A1 Substrate incorporating esd protection function
02/02/2011EP2280424A2 Method of aligning a patterned electrode in a selective emitter structure of a solar cell
02/02/2011EP2280413A2 Metal frame for electronic components
02/02/2011EP2280237A1 Heat sink having heat-dissipating fins of large area and method for manufacturing the same
02/02/2011EP2280236A1 Heat-dissipating fins, large-area heat sink having such heat-dissipating fins and method for manufacturing the same
02/02/2011EP2280044A1 Epoxy resin composition for encapsulating electronic part
02/02/2011EP2279522A1 Nanostructure-based heating devices and method of use
02/02/2011EP2279224A1 A curable composition and use thereof
02/02/2011EP2197780B1 Structure comprising a getter layer and an adjustment sublayer, and fabrication process
02/02/2011CN201733561U Ceramic substrate with metal coating
02/02/2011CN201733558U 散热器 Heat sink