Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
05/2011
05/04/2011CN101246874B Structure for interconnection and manufacture method
05/04/2011CN101227811B Vacuum super thermal conduction heat radiator
05/04/2011CN101218724B High current electrical switch and method
05/04/2011CN101179920B Apparatus and method for cooling heat-generating device
05/04/2011CN101159251B Microelectronic cooling assemblies and its manufacture method, and microelectronic cooling system
05/04/2011CN101047148B Manufacturing method of semiconductor device corresponding to loop back test
05/04/2011CN101001515B Plate radiating pipe and manufacturing method thereof
05/03/2011USRE42318 Semiconductor module with serial bus connection to multiple dies
05/03/2011US7937105 Semiconductor device and electronic device
05/03/2011US7936563 On-chip interconnect-stack cooling using sacrificial interconnect segments
05/03/2011US7936270 Space charge dosimeters for extremely low power measurements of radiation in shipping containers
05/03/2011US7936075 Semiconductor device and semiconductor device manufacturing method
05/03/2011US7936074 Programmable system in package
05/03/2011US7936073 Semiconductor device and method of manufacturing the same
05/03/2011US7936072 Semiconductor device having dual damascene structure
05/03/2011US7936071 Semiconductor device having a specified terminal layout pattern
05/03/2011US7936070 Semiconductor device and method for fabricating semiconductor device
05/03/2011US7936069 Semiconductor device with a line and method of fabrication thereof
05/03/2011US7936068 Semiconductor device having an interconnect structure and a reinforcing insulating film
05/03/2011US7936067 Backend interconnect scheme with middle dielectric layer having improved strength
05/03/2011US7936065 Semiconductor devices and method of manufacturing them
05/03/2011US7936063 Carrier assembly for an integrated circuit
05/03/2011US7936062 Wafer level chip packaging
05/03/2011US7936060 Reworkable electronic device assembly and method
05/03/2011US7936059 Lead frame packaging technique with reduced noise and cross-talk
05/03/2011US7936058 Stacked package and method for forming stacked package
05/03/2011US7936057 High bandwidth package
05/03/2011US7936056 Airtight package comprising a pressure adjustment unit
05/03/2011US7936055 Integrated circuit package system with interlock
05/03/2011US7936054 Multi-chip package
05/03/2011US7936053 Integrated circuit package system with lead structures including a dummy tie bar
05/03/2011US7936048 Power transistor and power semiconductor device
05/03/2011US7936045 Integrated circuit with multi-stage matching circuit
05/03/2011US7936030 Methods of operating semiconductor memory devices including magnetic films having electrochemical potential difference therebetween
05/03/2011US7936023 High voltage diode
05/03/2011US7936020 Dual-directional electrostatic discharge protection device
05/03/2011US7935998 Self-aligned body contact for a semiconductor-on-insulator trench device and method of fabricating same
05/03/2011US7935991 Semiconductor components with conductive interconnects
05/03/2011US7935965 Test structures and methods for electrical characterization of alignment of line patterns defined with double patterning
05/03/2011US7935953 Nonvolatile memory device, array of nonvolatile memory devices, and methods of making the same
05/03/2011US7935899 Circuit device and method of manufacturing the same
05/03/2011US7935627 Forming low dielectric constant dielectric materials
05/03/2011US7935623 Semiconductor device and method for fabricating the same
05/03/2011US7935622 Support with solder ball elements and a method for populating substrates with solder balls
05/03/2011US7935616 Dynamic p-n junction growth
05/03/2011US7935572 Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
05/03/2011US7935569 Components, methods and assemblies for stacked packages
05/03/2011US7935561 Method of forming shielded gate FET with self-aligned features
05/03/2011US7935430 Bonding structure of substrate and component and method of manufacturing the same
05/03/2011US7935408 Substrate anchor structure and method
05/03/2011CA2580031C System and method for assembling components in an electronic device
04/2011
04/28/2011WO2011050132A1 Improved microelectronic thermal interface
04/28/2011WO2011050073A1 Self-aligned barrier and capping layers for interconnects
04/28/2011WO2011049963A2 Method of embedding material in a glass substrate
04/28/2011WO2011049959A2 Methods and devices for manufacturing cantilever leads in a semiconductor package
04/28/2011WO2011049764A2 Leadframe packages having enhanced ground-bond reliability
04/28/2011WO2011049710A2 Stacked semiconductor device
04/28/2011WO2011049585A1 Esd/antenna diodes for through-silicon vias
04/28/2011WO2011049479A1 Composite material having high thermal conductivity and process of fabricating same
04/28/2011WO2011049128A1 Semiconductor device and method for manufacturing semiconductor device
04/28/2011WO2011049067A1 Substrate for power module, substrate with heat sink for power module, power module, method for producing substrate for power module, and method for producing substrate with heat sink for power module
04/28/2011WO2011048858A1 Device mounting structure and device mounting method
04/28/2011WO2011048800A1 Semiconductor device and process for production thereof
04/28/2011WO2011048765A1 Epoxy resin composition for semiconductor encapsulation, semiconductor device, and release agent
04/28/2011WO2011048580A1 Surge protection device
04/28/2011WO2011047792A1 Method for producing vias
04/28/2011WO2011047479A1 A routing layer for mitigating stress in a semiconductor die
04/28/2011WO2011047470A1 Reconfiguring through silicon vias in stacked multi-die packages
04/28/2011WO2011028348A3 Die location compensation
04/28/2011WO2011014434A3 Bond and probe pad distribution and package architecture
04/28/2011US20110098937 Integrated mos wireless sensor
04/28/2011US20110097848 Method for Connecting a Die Assembly to a Substrate in an Integrated Circuit and a Semiconductor Device Comprising a Die Assembly
04/28/2011US20110097826 Device and method for detecting stress migration properties
04/28/2011US20110097609 Method and apparatus for integrated-circuit battery devices
04/28/2011US20110097478 Scalable lead zirconium titanate (pzt) thin film material and deposition method, and ferroelectric memory device structures comprising such thin film material
04/28/2011US20110096604 Semiconductor memory device including alternately arranged contact members
04/28/2011US20110095441 Microelectronic assemblies having compliant layers
04/28/2011US20110095440 Semiconductor package including flip chip controller at bottom of die stack
04/28/2011US20110095439 Integrated circuit package system with through semiconductor vias and method of manufacture thereof
04/28/2011US20110095438 Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning
04/28/2011US20110095437 Interface plate between integrated circuits
04/28/2011US20110095436 Through silicon via with dummy structure and method for forming the same
04/28/2011US20110095435 Coaxial through-silicon via
04/28/2011US20110095434 Apparatus and methods of forming memory lines and structures using double sidewall patterning for four times half pitch relief patterning
04/28/2011US20110095433 Conductive film, method of manufacturing the same, semiconductor device and method of manufacturing the same
04/28/2011US20110095432 Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board and electronic instrument
04/28/2011US20110095431 Thermo-compression bonded electrical interconnect structure
04/28/2011US20110095430 Semiconductor device
04/28/2011US20110095429 Methods for fabricating and filling conductive vias and conductive vias so formed
04/28/2011US20110095428 Small area, robust silicon via structure and process
04/28/2011US20110095427 Low-resistance interconnects and methods of making same
04/28/2011US20110095426 Hybrid Package
04/28/2011US20110095425 Ball grid array substrate, semiconductor chip package and method of manufacturing the same
04/28/2011US20110095424 Semiconductor package structure
04/28/2011US20110095423 Semiconductor device mounted structure and its manufacturing method
04/28/2011US20110095422 Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
04/28/2011US20110095421 Flip chip package and method of manufacturing the same
04/28/2011US20110095420 Semiconductor device and method of manufacturing semiconductor device
04/28/2011US20110095419 Conductive film, method of manufacturing the same, semiconductor device and method of manufacturing the same
04/28/2011US20110095418 Semiconductor package and method for fabricating the same