Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
07/2011
07/19/2011US7982312 Method for fabricating dual damascene structures using photo-imprint lithography, methods for fabricating imprint lithography molds for dual damascene structures, materials for imprintable dielectrics and equipment for photo-imprint lithography used in dual damascene patterning
07/19/2011US7982311 Solder limiting layer for integrated circuit die copper bumps
07/19/2011US7982310 Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus
07/19/2011US7982309 includes a substrate including an active area and a gas phase deposited packaging material encapsulating the active area
07/19/2011US7982308 Light-emitting diode packaging structure and light-emitting diode module
07/19/2011US7982307 Integrated circuit chip assembly having array of thermally conductive features arranged in aperture of circuit substrate
07/19/2011US7982306 Stackable semiconductor package
07/19/2011US7982305 Integrated circuit package including a three-dimensional fan-out / fan-in signal routing
07/19/2011US7982304 Chip package structure
07/19/2011US7982303 Semiconductor device and communication method
07/19/2011US7982302 Power semiconductor module with control functionality and integrated transformer
07/19/2011US7982301 Semiconductor device
07/19/2011US7982300 Stackable layer containing ball grid array package
07/19/2011US7982299 Power semiconductor module
07/19/2011US7982298 Package in package semiconductor device
07/19/2011US7982297 Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same
07/19/2011US7982296 Methods and devices for fabricating and assembling printable semiconductor elements
07/19/2011US7982295 Electronic device, electronic apparatus mounted with electronic device, article equipped with electronic device and method of producing electronic device
07/19/2011US7982294 Semiconductor die with mask programmable interface selection
07/19/2011US7982293 Multi-chip package including die paddle with steps
07/19/2011US7982292 Semiconductor device
07/19/2011US7982291 Method for manufacturing a microelectromechanical component, and a microelectromechanical component
07/19/2011US7982290 Contact spring application to semiconductor devices
07/19/2011US7982285 Antifuse structure having an integrated heating element
07/19/2011US7982279 Method of manufacturing stacked-type semiconductor device
07/19/2011US7982271 Semiconductor device
07/19/2011US7982265 Trenched shield gate power semiconductor devices and methods of manufacture
07/19/2011US7982263 Semiconductor device having a plurality of misfets formed on a main surface of a semiconductor substrate
07/19/2011US7982245 Circuit with fuse/anti-fuse transistor with selectively damaged gate insulating layer
07/19/2011US7982235 Light emitting device, package and lead frame
07/19/2011US7981977 Sealant for electronics of epoxy resin, aromatic amine, accelerator and inorganic filler
07/19/2011US7981807 Manufacturing method of semiconductor device with smoothing
07/19/2011US7981792 Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
07/19/2011US7981769 Solid-state imaging device and method for manufacturing the same
07/19/2011US7981761 Method of manufacturing semiconductor device having MIM capacitor
07/19/2011US7981732 Programming of laser fuse
07/19/2011US7981731 Method of forming a high impedance antifuse
07/19/2011US7981730 Integrated conformal shielding method and process using redistributed chip packaging
07/19/2011US7981698 Removal of integrated circuits from packages
07/19/2011US7981574 Reticle, and method of laying out wirings and vias
07/19/2011US7981245 Forming plated through hole; surface roughness facilitates deposition of conductive metal; shrinkage inhibition
07/14/2011WO2011085260A2 Electronic devices and components for high efficiency power circuits
07/14/2011WO2011084706A2 Apparatus and method for controlling semiconductor die warpage
07/14/2011WO2011084235A2 Glass core substrate for integrated circuit devices and methods of making the same
07/14/2011WO2011084216A2 Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
07/14/2011WO2011084203A1 Method and apparatus for removing heat from electronic devices using synthetic jets
07/14/2011WO2011083753A1 Electronic component
07/14/2011WO2011083703A1 Led module device and method for manufacturing same
07/14/2011WO2011083652A1 Actinic-radiation curable composition and uses thereof
07/14/2011WO2011083578A1 Semiconductor module
07/14/2011WO2011083368A1 Delamination resistant semiconductor devices
07/14/2011WO2011083052A1 Thermal plug for use with a heat sink and method of assembling same
07/14/2011WO2011082874A1 Tunnel junction via
07/14/2011WO2011061695A3 Apparatus and method for processing a substrate
07/14/2011WO2011028042A3 Packing material containing tungsten and integrated package
07/14/2011US20110171828 Semiconductor device with a line and method of fabrication thereof
07/14/2011US20110171825 Method of Fabricating Integrated Circuitry
07/14/2011US20110171824 Semiconductor device and method for fabricating the same
07/14/2011US20110171780 Semiconductor device and manufacturing method thereof
07/14/2011US20110170328 Semiconductor memory device
07/14/2011US20110169564 Integrated Circuit
07/14/2011US20110169562 System on chip power management through package configuration
07/14/2011US20110169175 Overlay mark
07/14/2011US20110169174 Method for fabricating semiconductor device
07/14/2011US20110169173 Wiring substrate for a semiconductor chip and semiconducotor package having the wiring substrate
07/14/2011US20110169172 Semiconductor Device having dual damascene structure
07/14/2011US20110169171 Dual Interconnection in Stacked Memory and Controller Module
07/14/2011US20110169170 Semiconductor device
07/14/2011US20110169169 Method for providing and connecting two contact areas of a semiconductor component or a substrate, and a substrate having two such connected contact areas
07/14/2011US20110169168 Through-silicon via formed with a post passivation interconnect structure
07/14/2011US20110169167 Grid array connection device and method
07/14/2011US20110169166 Semiconductor device sealed in a resin section and method for manufacturing the same
07/14/2011US20110169165 Semiconductor device
07/14/2011US20110169164 Wiring substrate, manufacturing method thereof, and semiconductor package
07/14/2011US20110169163 Attaching passive components to a semiconductor package
07/14/2011US20110169162 Integrated Circuit Module and Multichip Circuit Module Comprising an Integrated Circuit Module of This Type
07/14/2011US20110169161 Semiconductor device
07/14/2011US20110169160 Real time monitoring of indium bump reflow and oxide removal enabling optimization of indium bump morphology
07/14/2011US20110169159 Chip package and fabrication method thereof
07/14/2011US20110169158 Solder Pillars in Flip Chip Assembly
07/14/2011US20110169157 Substrate and flip chip package with gradational pad pitches
07/14/2011US20110169156 Semiconductor package and manufacturing method thereof and encapsulating method thereof
07/14/2011US20110169155 Semiconductor apparatus with lid bonded on wiring board and method of manufacturing the same
07/14/2011US20110169154 Microelectronic devices and methods for manufacturing microelectronic devices
07/14/2011US20110169153 Lead frame substrate and method of manufacturing the same
07/14/2011US20110169152 Semiconductor package
07/14/2011US20110169151 Integrated circuit packaging system with lead interlocking mechanisms and method of manufacture thereof
07/14/2011US20110169150 Semiconductor Package with Single Sided Substrate Design and Manufacturing Methods Thereof
07/14/2011US20110169149 Semiconductor package system with fine pitch lead fingers and method of manufacturing thereof
07/14/2011US20110169148 Tape wiring substrate and tape package using the same
07/14/2011US20110169147 Chip package structure and package substrate
07/14/2011US20110169146 Contactless communication medium
07/14/2011US20110169145 Manufacturing method of lead frame substrate and semiconductor apparatus
07/14/2011US20110169144 Die package including multiple dies and lead orientation
07/14/2011US20110169143 Method for establishing and closing a trench of a semiconductor component
07/14/2011US20110169142 Semiconductor device and method for manufacturing the same
07/14/2011US20110169141 Insulating layers on different semiconductor materials
07/14/2011US20110169140 Reclaiming usable integrated circuit chip area near through-silicon vias
07/14/2011US20110169139 Chip package and fabrication method thereof
07/14/2011US20110169133 Wiring substrate, method for manufacturing wiring substrate, and semiconductor package including wiring substrate