Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
01/2012
01/26/2012WO2012010469A1 Electronic assembly having a component enclosed by a potting compound, and method for producing same
01/26/2012WO2012009848A1 Pre-solder method and rework method for multi-row qfn chip
01/26/2012WO2012009831A1 Wiring board and manufacturing method thereof
01/26/2012WO2011152363A3 Method for producing ceramic for heat-radiating members, ceramic for heat-radiating members, and solar cell module and led light-emitting module using said ceramic
01/26/2012WO2011139496A3 Techniques for interconnecting stacked dies using connection sites
01/26/2012WO2011133743A3 Interleaf for leadframe identification
01/26/2012WO2011130252A3 Ball-grid array device having chip assembled on half-etched metal leadframe
01/26/2012WO2011087485A3 Microelectronic assembly with joined bond elements having lowered inductance
01/26/2012WO2011064221A3 Sensor module and production method of a sensor module
01/26/2012US20120021602 Low resistance and reliable copper interconnects by variable doping
01/26/2012US20120021598 Method for fabricating semiconductor device
01/26/2012US20120019292 Configuration of a multi-die integrated circuit
01/26/2012US20120018906 Circuit device and method of manufacturing the same
01/26/2012US20120018905 Electronic component assembly having profiled encapsulated bonds
01/26/2012US20120018903 Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device
01/26/2012US20120018902 Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device
01/26/2012US20120018901 Flip-chip package and method of manufacturing the same using ablation
01/26/2012US20120018900 Semiconductor Device and Method of Conforming Conductive Vias Between Insulating Layers in Saw Streets
01/26/2012US20120018899 Semiconductor Device and Method of Conforming Conductive Vias Between Insulating Layers in Saw Streets
01/26/2012US20120018898 Via structure and method thereof
01/26/2012US20120018897 Semiconductor module and method of manufacturing the same
01/26/2012US20120018896 Semiconductor device
01/26/2012US20120018895 Active chip on carrier or laminated chip having microelectronic element embedded therein
01/26/2012US20120018894 Non-lithographic formation of three-dimensional conductive elements
01/26/2012US20120018893 Methods of forming semiconductor elements using micro-abrasive particle stream
01/26/2012US20120018892 Semiconductor device with inductor and flip-chip
01/26/2012US20120018891 Methods to form self-aligned permanent on-chip interconnect structures
01/26/2012US20120018890 Semiconductor device
01/26/2012US20120018889 Process for producing a metallization level and a via level and corresponding integrated circuit
01/26/2012US20120018887 Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
01/26/2012US20120018886 Integrated circuit package with open substrate and method of manufacturing thereof
01/26/2012US20120018885 Semiconductor apparatus having through vias
01/26/2012US20120018884 Semiconductor package structure and forming method thereof
01/26/2012US20120018883 Conductive structure for a semiconductor integrated circuit
01/26/2012US20120018882 Semiconductor Device and Method of Forming Stress Relief Layer Between Die and Interconnect Structure
01/26/2012US20120018881 Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structure
01/26/2012US20120018880 Semiconductor structure and manufacturing method thereof
01/26/2012US20120018877 Package-on-Package Structures with Reduced Bump Bridging
01/26/2012US20120018876 Multi-Die Stacking Using Bumps with Different Sizes
01/26/2012US20120018875 Reducing Delamination Between an Underfill and a Buffer layer in a Bond Structure
01/26/2012US20120018874 Semiconductor Device and Method of Forming RDL over Contact Pad with High Alignment Tolerance or Reduced Interconnect Pitch
01/26/2012US20120018873 Method and package for circuit chip packaging
01/26/2012US20120018872 Lid for an electrical hardware component
01/26/2012US20120018871 Stack package and semiconductor package including the same
01/26/2012US20120018870 Chip scale package and fabrication method thereof
01/26/2012US20120018869 Mold design and semiconductor package
01/26/2012US20120018868 Microelectronic elements having metallic pads overlying vias
01/26/2012US20120018867 Substrate for semiconductor element, method for manufacturing substrate for semiconductor element, and semiconductor device
01/26/2012US20120018866 Integrated circuit packaging system with island terminals and method of manufacture thereof
01/26/2012US20120018865 Integrated circuit packaging system with island terminals and embedded paddle and method of manufacture thereof
01/26/2012US20120018864 Bonding structure and method
01/26/2012US20120018863 Microelectronic elements with rear contacts connected with via first or via middle structures
01/26/2012US20120018862 Semiconductor package
01/26/2012US20120018861 Tape carrier substrate
01/26/2012US20120018860 Method for manufacturing substrate for semiconductor element, and semiconductor device
01/26/2012US20120018859 Semiconductor device and method of manufacturing the same
01/26/2012US20120018858 Method of assembling integrated circuit device
01/26/2012US20120018857 System and method of chip package build-up
01/26/2012US20120018854 Semiconductor device and the method of manufacturing the same
01/26/2012US20120018852 Via structure and method thereof
01/26/2012US20120018851 Metal-contamination-free through-substrate via structure
01/26/2012US20120018841 Semiconductor device
01/26/2012US20120018726 Semiconductor wafer and method for manufacturing semiconductor device
01/26/2012US20120018723 Structure and method for testing through-silicon via (tsv)
01/26/2012DE10357789B4 Leistungs-Halbleitervorrichtung Power semiconductor device
01/26/2012DE102011079768A1 Halbleiterbauelement mit Driftgebieten und Kompensationsgebieten Semiconductor component with drift compensation areas and areas
01/26/2012DE102010038362A1 Kontaktelement Contact member
01/26/2012DE102010026529A1 Kühlkörper mit einem elektrischen Bauteil Heat sink with an electrical component
01/26/2012DE102009039247B9 Halbleiterkörper mit einer Anschlusszelle Semiconductor body having a connection cell
01/26/2012DE102007016901B4 Halbleiterbauelement und elektronisches Modul Semiconductor device and electronic module
01/26/2012DE102006047989B4 Leistungshalbleitervorrichtung und Verfahren zu deren Herstellung Power semiconductor device and process for their preparation
01/26/2012DE102006022066B4 ESD-Schutzschaltung ESD protection circuit
01/26/2012DE102006011697B4 Integrierte Halbleiterbauelementeanordnung und Verfahren zu deren Herstellung Integrated semiconductor device assembly and method for their preparation
01/26/2012DE102004062635B4 Elektrische Baugruppe mit Abstandshaltern zwischen mehreren Schaltungsträgern The electrical assembly with spacers between multiple circuit boards
01/26/2012DE102004024887B4 Transistor mit Zellenfeld, Temperatursensor und Isolationsstruktur Transistor cell array, temperature sensor and isolation structure
01/25/2012EP2410827A1 Circuit board and mother laminated body
01/25/2012EP2410565A1 Component to connection to an antenna
01/25/2012EP2410564A2 Non-circular radial heat sink
01/25/2012EP2410563A2 Stacked interconnect heat sink
01/25/2012EP2410562A1 Semiconductor device, method for manufacturing same, electronic device and electronic component
01/25/2012EP2410561A1 Circuit module and electronic device
01/25/2012EP2410078A1 Coating and electronic component
01/25/2012EP2410001A1 Inclusion complex, curing agent, cure accelerator, epoxy resin composition, and epoxy resin composition for encapsulation of semiconductor
01/25/2012EP2409979A1 Process for production of phosphorus-atom-containing phenol, novel phosphorus-atom-containing phenol, curable resin composition, cured product thereof, printed circuit board, and semiconductor sealing material
01/25/2012EP2409662A2 Electrosurgical systems and printed circuit boards for use therewith
01/25/2012EP2409328A1 Multi-die semiconductor package with heat spreader
01/25/2012EP2409327A1 Vertically contacted electronic component and method for producing same
01/25/2012EP2409326A2 Rapid fabrication of a microelectronic temporary support for inorganic substrates
01/25/2012EP2408942A1 A method for the removal of hydrogen from a hydrogen sensitive device by means of a non-evaporable yttrium based getter alloy
01/25/2012EP2269219B1 High frequency field-effect transistor
01/25/2012EP2074653B1 Plastic surface mount large area power semiconductor device
01/25/2012EP1889262B1 Anti-fuse memory device
01/25/2012EP1461815B1 Material deposition from a liquefied gas solution
01/25/2012EP1376696B1 Semiconductor device
01/25/2012EP1303880B1 Method for applying adjustment marks on a semiconductor disk
01/25/2012CN202127018U Mitsubishi cooling fin structure for rectifier bridge of alternating-current generator for vehicle
01/25/2012CN202127016U 16-row lead frame
01/25/2012CN202127015U Lead frame with blank holders at backs of matrixes
01/25/2012CN202127014U Frame for two rows of leads used for plastic package devices of light-operated devices and voice-controlled devices
01/25/2012CN202127013U Semiconductor lead frame of whole substrate surface