Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 23 - Details of semiconductor or other solid state devices
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
07/2012
07/03/2012US8212344 Microelectromechanical semiconductor component with cavity structure and method for producing the same
07/03/2012US8212343 Semiconductor chip package
07/03/2012US8212342 Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof
07/03/2012US8212341 Apparatus and methods for packaging integrated circuit chips with antennas formed from package lead wires
07/03/2012US8212340 Chip package and manufacturing method thereof
07/03/2012US8212339 Semiconductor device packages with electromagnetic interference shielding
07/03/2012US8212337 Advanced low k cap film formation process for nano electronic devices
07/03/2012US8212335 Semiconductor substrate having a flexible, heat resistant, graphite substrate
07/03/2012US8212331 Method for fabricating a backside through-wafer via in a processed wafer and related structure
07/03/2012US8212330 Process for improving the reliability of interconnect structures and resulting structure
07/03/2012US8212329 Short channel lateral MOSFET and method
07/03/2012US8212323 Seal ring structure for integrated circuits
07/03/2012US8212320 High voltage tolerant ESD device
07/03/2012US8212286 Semiconductor light receiving element
07/03/2012US8212279 Semiconductor chip assembly with post/base heat spreader, signal post and cavity
07/03/2012US8211791 Method for fabricating circuitry component
07/03/2012US8211755 Method for multi-level interconnection memory device
07/03/2012US8211753 Leadframe-based mold array package heat spreader and fabrication method therefor
07/03/2012US8211750 Semiconductor device comprising light-emitting element and light-receiving element, and manufacturing method therefor
07/03/2012US8211745 Method and structure for bonding flip chip
07/03/2012US8211740 Solid state imaging device having wirings with diffusion prevention film
07/03/2012US8211540 Adhesive film composition, associated dicing die bonding film, die package, and associated methods
07/03/2012US8211538 Microelectronic security coatings
07/03/2012US8211238 System, method and apparatus for self-cleaning dry etch
07/03/2012US8210120 Systems and methods for building tamper resistant coatings
07/03/2012CA2512845C Semiconductor package having non-ceramic based window frame
06/2012
06/28/2012WO2012088480A2 Thermal loading mechanism
06/28/2012WO2012087915A1 Electronic device submounts including substrates with thermally conductive vias
06/28/2012WO2012087613A2 Fabrication of through-silicon vias on silicon wafers
06/28/2012WO2012087556A2 Device packaging with substrates having embedded lines and metal defined pads
06/28/2012WO2012087552A1 Reduced plated through hole (pth) pad for enabling core routing and substrate layer count reduction
06/28/2012WO2012087475A2 Substrate with embedded stacked through-silicon via die
06/28/2012WO2012087474A2 A multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same
06/28/2012WO2012086871A1 Semiconductor chip stack package and manufacturing method thereof
06/28/2012WO2012086724A1 Connected substrate, method of manufacturing thereof, element substrate, and light-emitting apparatus
06/28/2012WO2012086464A1 Power module and lead frame for power module
06/28/2012WO2012086463A1 Curable epoxy resin composition and photosemiconductor device using same
06/28/2012WO2012086417A1 Insulating structure for power module and power conversion device using power module
06/28/2012WO2012086058A1 Cooler
06/28/2012WO2012085952A1 Assembly for the heat dissipation and the electrical connection of current-rectifier button diodes
06/28/2012WO2012084743A1 Method for producing an electrical terminal support
06/28/2012WO2012084736A1 Method for obtaining a palladium surface finish for copper wire bonding on printed circuit boards and ic-substrates
06/28/2012WO2012084671A1 Porous heat sink led lamps
06/28/2012WO2012084436A1 Cooling system and method for electronic components
06/28/2012WO2012084207A1 Connection structure for an integrated circuit with capacitive function
06/28/2012WO2012083955A1 Single-position hall effect measurements
06/28/2012WO2012051435A3 Shield-modulated tunable inductor device
06/28/2012WO2012022404A3 Core-sheath ribbon wire
06/28/2012US20120163954 Module for use in stacking the thin plate panel and method of stacking the thin plate panel
06/28/2012US20120163937 Solar panel racking system and transport mechanism
06/28/2012US20120162947 Vertically integrated systems
06/28/2012US20120161856 Die power structure
06/28/2012US20120161339 Fiber-containing resin substrate, sealed substrate having semiconductor device mounted thereon, sealed wafer having semiconductor device formed thereon, a semiconductor apparatus, and method for manufacturing semiconductor apparatus
06/28/2012US20120161338 Printable Composition of a Liquid or Gel Suspension of Two-Terminal Integrated Circuits and Apparatus
06/28/2012US20120161337 Wiring method for semiconductor integrated circuit, semiconductor-circuit wiring apparatus and semiconductor integrated circuit
06/28/2012US20120161336 Semiconductor device and assembling method thereof
06/28/2012US20120161335 Semiconductor device and method of manufacturing the same
06/28/2012US20120161334 Redundancy design with electro-migration immunity and method of manufacture
06/28/2012US20120161333 Device for connecting nano-objects to external electrical systems, and method for producing said device
06/28/2012US20120161332 Method for producing vias in fan-out wafers using dry film and conductive paste, and a corresponding semiconductor package
06/28/2012US20120161331 Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same
06/28/2012US20120161330 Device packaging with substrates having embedded lines and metal defined pads
06/28/2012US20120161329 Multi-level integrated circuit, device and method for modeling multi-level integrated circuits
06/28/2012US20120161328 Reticle set modification to produce multi-core dies
06/28/2012US20120161327 Shrinkage of Contact Elements and Vias in a Semiconductor Device by Incorporating Additional Tapering Material
06/28/2012US20120161326 Composition for filling through silicon via (tsv), tsv filling method and substrate including tsv plug formed of the composition
06/28/2012US20120161325 Semiconductor device package
06/28/2012US20120161324 Semiconductor Device Comprising Contact Elements with Silicided Sidewall Regions
06/28/2012US20120161323 Substrate for package and method for manufacturing the same
06/28/2012US20120161321 Semiconductor device contacts
06/28/2012US20120161320 Cobalt metal barrier layers
06/28/2012US20120161319 Ball grid array method and structure
06/28/2012US20120161318 Multilayer dielectric memory device
06/28/2012US20120161317 Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection
06/28/2012US20120161316 Substrate with embedded stacked through-silicon via die
06/28/2012US20120161315 Three-dimensional system-in-package package-on-package structure
06/28/2012US20120161314 Template wafer and process for small pitch flip-chip interconnect hybridization
06/28/2012US20120161313 Semiconductor device, and inspection method thereof
06/28/2012US20120161312 Non-solder metal bumps to reduce package height
06/28/2012US20120161311 Wiring board and semiconductor package
06/28/2012US20120161310 Trap Rich Layer for Semiconductor Devices
06/28/2012US20120161309 Semiconductor package
06/28/2012US20120161308 Protecting T-Contacts of Chip Scale Packages from Moisture
06/28/2012US20120161307 Chip scale surface mounted semiconductor device package and process of manufacture
06/28/2012US20120161306 Semiconductor Package
06/28/2012US20120161305 Techniques for bonding substrates using an intermediate layer
06/28/2012US20120161304 Dual-leadframe Multi-chip Package and Method of Manufacture
06/28/2012US20120161303 Power semiconductor module
06/28/2012US20120161302 Semiconductor device and method for manufacturing the same
06/28/2012US20120161301 Semiconductor package and fabrication method thereof
06/28/2012US20120161300 Ionizing radiation blocking in ic chip to reduce soft errors
06/28/2012US20120161299 Interlevel conductive light shield
06/28/2012US20120161297 Semiconductor device and method for manufacturing the same
06/28/2012US20120161294 Method of Batch Trimming Circuit Elements
06/28/2012US20120161278 Method and system for providing fusing after packaging of semiconductor devices
06/28/2012US20120161275 Methods for forming a bonded semiconductor substrate including a cooling mechanism
06/28/2012US20120161216 ESD Protection Circuit
06/28/2012US20120161190 Electronic device submounts including substrates with thermally conductive vias
06/28/2012US20120161129 Method and apparatus of fabricating a pad structure for a semiconductor device
06/28/2012US20120161128 Die package
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