| Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155) |
|---|
| 01/29/2013 | US8362617 Semiconductor device |
| 01/29/2013 | US8362616 Semiconductor device having plurality of wiring layers and designing method thereof |
| 01/29/2013 | US8362614 Fine pitch grid array type semiconductor device |
| 01/29/2013 | US8362613 Flip chip device having simplified routing |
| 01/29/2013 | US8362611 Semiconductor module, method for manufacturing semiconductor module, and portable device |
| 01/29/2013 | US8362610 Mounting configuration of electronic component |
| 01/29/2013 | US8362609 Integrated circuit package and method of forming an integrated circuit package |
| 01/29/2013 | US8362608 Ultra wideband hermetically sealed surface mount technology for microwave monolithic integrated circuit package |
| 01/29/2013 | US8362607 Integrated circuit package including a thermally and electrically conductive package lid |
| 01/29/2013 | US8362606 Wafer level chip scale package |
| 01/29/2013 | US8362605 Apparatus and method for use in mounting electronic elements |
| 01/29/2013 | US8362603 Flexible circuit light-emitting structures |
| 01/29/2013 | US8362602 Layered chip package and method of manufacturing same |
| 01/29/2013 | US8362601 Wire-on-lead package system having leadfingers positioned between paddle extensions and method of manufacture thereof |
| 01/29/2013 | US8362600 Method and structure to reduce soft error rate susceptibility in semiconductor structures |
| 01/29/2013 | US8362599 Forming radio frequency integrated circuits |
| 01/29/2013 | US8362598 Semiconductor device with electromagnetic interference shielding |
| 01/29/2013 | US8362597 Shielded package having shield lid |
| 01/29/2013 | US8362596 Engineered interconnect dielectric caps having compressive stress and interconnect structures containing same |
| 01/29/2013 | US8362588 Semiconductor chip with coil element over passivation layer |
| 01/29/2013 | US8362576 Transistor with reduced depletion field width |
| 01/29/2013 | US8362575 Controlling the shape of source/drain regions in FinFETs |
| 01/29/2013 | US8362559 Hybrid molecular electronic devices containing molecule-functionalized surfaces for switching, memory, and sensor applications and methods for fabricating same |
| 01/29/2013 | US8362524 Semiconductor device having a fuse element |
| 01/29/2013 | US8362486 Solid state image pickup device and method of producing solid state image pickup device |
| 01/29/2013 | US8362481 Ultra high speed signal transmission/reception |
| 01/29/2013 | US8362115 Epoxy resin composition |
| 01/29/2013 | US8361886 Method for programming an anti-fuse element, and semiconductor device |
| 01/29/2013 | US8361881 Method for alternately contacting two wafers |
| 01/29/2013 | US8361877 Manufacturing method of semiconductor device, semiconductor device, and method of printing on semiconductor wafer |
| 01/29/2013 | US8361843 Method for fabricating heat dissipation package structure |
| 01/29/2013 | US8361839 Structure and method for power field effect transistor |
| 01/29/2013 | US8361838 Semiconductor package and method for manufacturing the same via holes in semiconductor chip for plurality stack chips |
| 01/29/2013 | US8361829 On-chip radiation dosimeter |
| 01/29/2013 | US8361598 Substrate anchor structure and method |
| 01/24/2013 | WO2013013204A2 Interconnect pillars with directed compliance geometry |
| 01/24/2013 | WO2013012852A1 Resilient mounting assembly for photovoltaic modules |
| 01/24/2013 | WO2013012682A2 Copper interconnects separated by air gaps and method of making thereof |
| 01/24/2013 | WO2013012634A2 Double-sided flip chip package |
| 01/24/2013 | WO2013012587A2 Semiconductor package resin composition and usage method thereof |
| 01/24/2013 | WO2013012455A1 Substrate for integrated modules |
| 01/24/2013 | WO2013012450A1 Inductive structure formed using through silicon vias |
| 01/24/2013 | WO2013011850A1 Method for manufacturing electronic component and adhesive sheet used in method for manufacturing electronic component |
| 01/24/2013 | WO2013011832A1 Curable epoxy resin composition |
| 01/24/2013 | WO2013011682A1 Cooling apparatus, electronic apparatus provided with same, and electric vehicle |
| 01/24/2013 | WO2013011668A1 Composite material for heat dissipating substrate, and method for manufacturing composite material for heat dissipating substrate |
| 01/24/2013 | WO2013011636A1 Installation structure for coolant pipe |
| 01/24/2013 | WO2013010870A1 Method for forming a composite material, and heat sink |
| 01/24/2013 | WO2013010353A1 Low-k chip packaging structure |
| 01/24/2013 | WO2013010352A1 Method for packaging low-k chip |
| 01/24/2013 | US20130021768 Chip-on-film packages and device assemblies including the same |
| 01/24/2013 | US20130021760 Multi-channel package and electronic system including the same |
| 01/24/2013 | US20130020929 Solid state lighting device including green shifted red component |
| 01/24/2013 | US20130020725 Semiconductor device and method of manufacturing semiconductor device |
| 01/24/2013 | US20130020724 Manufacturing method of semiconductor device, adhesive sheet used therein, and semiconductor device obtained thereby |
| 01/24/2013 | US20130020723 Composite layered chip package |
| 01/24/2013 | US20130020722 Semiconductor device, circuit substrate, and electronic device |
| 01/24/2013 | US20130020721 Semiconductor device and method for manufacturing the same |
| 01/24/2013 | US20130020719 Microelectronic devices including through silicon via structures having porous layers |
| 01/24/2013 | US20130020718 MEMS Devices and Methods of Forming Same |
| 01/24/2013 | US20130020717 Integrated circuit having a stressor and method of forming the same |
| 01/24/2013 | US20130020716 System and method to process horizontally aligned graphite nanofibers in a thermal interface material used in 3d chip stacks |
| 01/24/2013 | US20130020715 Semiconductor Device |
| 01/24/2013 | US20130020714 Contact pad |
| 01/24/2013 | US20130020713 Wafer Level Package and a Method of Forming a Wafer Level Package |
| 01/24/2013 | US20130020712 Implementing integrated circuit mixed double density and high performance wire structure |
| 01/24/2013 | US20130020711 Interconnect Pillars with Directed Compliance Geometry |
| 01/24/2013 | US20130020709 Semiconductor package and method of fabricating the same |
| 01/24/2013 | US20130020708 Copper Interconnects Separated by Air Gaps and Method of Making Thereof |
| 01/24/2013 | US20130020707 Novel semiconductor system and device |
| 01/24/2013 | US20130020706 Semiconductor device and manufacturing method thereof |
| 01/24/2013 | US20130020705 Method to form uniform silicide by selective implantation |
| 01/24/2013 | US20130020704 Bonding surfaces for direct bonding of semiconductor structures |
| 01/24/2013 | US20130020703 Method for Making a Stackable Package |
| 01/24/2013 | US20130020702 Double-sided flip chip package |
| 01/24/2013 | US20130020701 Semiconductor device and a method of manufacturing the same |
| 01/24/2013 | US20130020700 Chip package and fabrication method thereof |
| 01/24/2013 | US20130020699 Package structure and method for fabricating the same |
| 01/24/2013 | US20130020698 Pillar Design for Conductive Bump |
| 01/24/2013 | US20130020697 Techniques and structures for testing integrated circuits in flip-chip assemblies |
| 01/24/2013 | US20130020696 Semiconductor device |
| 01/24/2013 | US20130020695 "L" Shaped Lead Integrated Circuit Package |
| 01/24/2013 | US20130020694 Power module packaging with double sided planar interconnection and heat exchangers |
| 01/24/2013 | US20130020692 Semiconductor device and method of manufacturing the same |
| 01/24/2013 | US20130020691 Method of Manufacturing a Semiconductor Device |
| 01/24/2013 | US20130020690 Stacked die semiconductor package |
| 01/24/2013 | US20130020689 Semiconductor device and method of packaging same |
| 01/24/2013 | US20130020688 Chip package structure and manufacturing method thereof |
| 01/24/2013 | US20130020687 Power module package and method for manufacturing the same |
| 01/24/2013 | US20130020686 Package structure and package process |
| 01/24/2013 | US20130020685 Substrates for semiconductor devices including internal shielding structures and semiconductor devices including the substrates |
| 01/24/2013 | US20130020683 Substrate for semiconductor package and semiconductor package having the same |
| 01/24/2013 | US20130020675 Inductive structure formed using through silicon vias |
| 01/24/2013 | US20130020674 Fused buss for plating features on a semiconductor die |
| 01/24/2013 | US20130020647 Semiconductor devices and methods of fabricating the same |
| 01/24/2013 | US20130020572 Cap Chip and Reroute Layer for Stacked Microelectronic Module |
| 01/24/2013 | US20130020468 Solid-state imaging device, manufacturing method of solid-state imaging device, manufacturing method of semiconductor device, semiconductor device, and electronic device |
| 01/24/2013 | DE112011100484T5 Wärmeableitungsstruktur eines SOI-Feldeffekttransistors Heat dissipation structure of an SOI field effect transistor |
| 01/24/2013 | DE112010005279T5 Vorrichtung für elastische Wellen A device for elastic waves |
| 01/24/2013 | DE112010004589T5 Laminat und Herstellungsverfahren hierfür Laminate and production process thereof |