Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
02/2013
02/26/2013US8384204 Circuit carrier and semiconductor package using the same
02/26/2013US8384203 Packaging structural member
02/26/2013US8384202 Semiconductor device, and communication apparatus and electronic apparatus having the same
02/26/2013US8384201 Wafer and method for improving yield rate of wafer
02/26/2013US8384200 Semiconductor device assemblies including face-to-face semiconductor dice and systems including such assemblies
02/26/2013US8384199 Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
02/26/2013US8384197 Semiconductor device and method for manufacturing same
02/26/2013US8384189 High performance system-on-chip using post passivation process
02/26/2013US8384185 Semiconductor device and a method of manufacturing the same
02/26/2013US8384158 Chip and electrostatic discharge protection device thereof
02/26/2013US8384132 System for separation of an electrically conductive connection
02/26/2013US8384117 Light emitting device package and lighting system including the same
02/26/2013US8384116 Substrate with chips mounted thereon, method of manufacturing substrate with chips mounted thereon, display, and method of manufacturing display
02/26/2013US8384103 Increasing contrast in electronic color displays via surface texturing of LEDs
02/26/2013US8383964 Terminal structure, printed wiring board, module substrate, and electronic device
02/26/2013US8383962 Exposed die pad package with power ring
02/26/2013US8383949 Method to form lateral pad on edge of wafer
02/26/2013US8383514 Method for stacking serially-connected integrated circuits and multi-chip device made from same
02/26/2013US8383507 Method for fabricating air gap interconnect structures
02/26/2013US8383478 High-density nonvolatile memory and methods of making the same
02/26/2013US8383462 Method of fabricating an integrated circuit package
02/26/2013US8383458 Integrated circuit package system employing an offset stacked configuration and method for manufacturing thereof
02/26/2013US8383007 Seeding resins for enhancing the crystallinity of polymeric substructures
02/26/2013CA2550015C Metal-based carbon fiber composite material and method for producing the same
02/21/2013WO2013025982A1 Liquid cooling of stacked die through substrate lamination
02/21/2013WO2013025981A2 Selective plating of frame lid assembly
02/21/2013WO2013025728A1 Semiconductor laser mounting with intact diffusion barrier layer
02/21/2013WO2013025573A2 Solder bump bonding in semiconductor package using solder balls having high-temperature cores
02/21/2013WO2013025338A1 Multi-chip package and interposer with signal line compression
02/21/2013WO2013025205A1 Offset interposers for large-bottom packages and large-die package-on-package structures
02/21/2013WO2013025130A1 Heat removal device
02/21/2013WO2013024813A1 Substrate for power module, substrate for power module with heat sink, power module, and method for manufacturing substrate for power module
02/21/2013WO2013024677A1 Semiconductor device, manufacturing method thereof, and mobile telephone
02/21/2013WO2013024561A1 Light-emitting device
02/21/2013WO2013024560A1 Light-emitting device
02/21/2013WO2013023388A1 Embeded circuit board and method for manufacturing the same
02/21/2013WO2013023386A1 Chip on film tape baseplate of liquid crystal panel, and liquid crystal panel
02/21/2013WO2013023360A1 Test pin array with electrostatic discharge protection
02/21/2013WO2013023321A1 Mixing manifold and method
02/21/2013WO2012175627A3 Thermal management system with variable-volume material
02/21/2013WO2012143770A3 Cooling fin structure
02/21/2013US20130045572 Flexible routing for high current module application
02/21/2013US20130045329 Manufacturing method thereof and a semiconductor device
02/21/2013US20130043940 Back-to-back stacked dies
02/21/2013US20130043897 Testing stacked die
02/21/2013US20130043604 Semiconductor device and method for manufacturing the same
02/21/2013US20130043603 Method of forming a conductive image on a non-conductive surface
02/21/2013US20130043602 Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer
02/21/2013US20130043601 Universal printed circuit board and memory card including the same
02/21/2013US20130043600 Bonded semiconductor structures including two or more processed semiconductor structures carried by a common substrate
02/21/2013US20130043599 Chip package process and chip package structure
02/21/2013US20130043598 Bond pad structure to reduce bond pad corrosion
02/21/2013US20130043597 Semiconductor Constructions and Methods of Forming Interconnects
02/21/2013US20130043596 Semiconductor device
02/21/2013US20130043595 Semiconductor Package Containing Silicon-On-Insulator Die Mounted In Bump-On-Leadframe Manner To Provide Low Thermal Resistance
02/21/2013US20130043594 Method for manufacturing semiconductor device and semiconductor device
02/21/2013US20130043593 Semiconductor Arrangement
02/21/2013US20130043591 Tungsten metallization: structure and fabrication of same
02/21/2013US20130043590 Semiconductor structure and method of manufacturing
02/21/2013US20130043589 Methods of Forming a Non-Planar Cap Layer Above Conductive Lines on a Semiconductor Device
02/21/2013US20130043588 Semiconductor dice including at least one blind hole, wafers including such semiconductor dice, and intermediate products made while forming at least one blind hole in a substrate
02/21/2013US20130043587 Package-on-package structures
02/21/2013US20130043586 Method for encapsulating electronic components on a wafer
02/21/2013US20130043585 Semiconductor apparatus, method of manufacturing semiconductor apparatus, and electronic apparatus
02/21/2013US20130043584 Semiconductor devices, package substrates, semiconductor packages, package stack structures, and electronic systems having functionally asymmetric conductive elements
02/21/2013US20130043583 Dummy Flip Chip Bumps for Reducing Stress
02/21/2013US20130043582 Multiple die in a face down package
02/21/2013US20130043581 Semiconductor device
02/21/2013US20130043579 Power semiconductor arrangement, power semiconductor module with multiple power semiconductor arrangements, and module assembly comprising multiple power semiconductor modules
02/21/2013US20130043578 Presspin, power semiconducter module and semiconducter module assembly with multiple power semiconducter modules
02/21/2013US20130043577 Manufacturing method thereof and a semiconductor device
02/21/2013US20130043576 Semiconductor device
02/21/2013US20130043575 Chip-packaging module for a chip and a method for forming a chip-packaging module
02/21/2013US20130043574 Multi-Die Semiconductor Package With One Or More Embedded Die Pads
02/21/2013US20130043573 Solder Bump Bonding In Semiconductor Package Using Solder Balls Having High-Temperature Cores
02/21/2013US20130043572 Bump-On-Leadframe Semiconductor Package With Low Thermal Resistance
02/21/2013US20130043571 Power overlay structure with leadframe connections
02/21/2013US20130043570 Chip package and method for forming the same
02/21/2013US20130043569 Integrated Circuit Devices and Methods and Apparatuses for Designing Integrated Circuit Devices
02/21/2013US20130043568 Memory device and a fabricating method thereof
02/21/2013US20130043566 Semiconductor device and flip-chip package
02/21/2013US20130043565 Integrated circuit system with sub-geometry removal and method of manufacture thereof
02/21/2013US20130043556 Size-filtered multimetal structures
02/21/2013US20130043541 Low power/high speed tsv interface design
02/21/2013US20130043514 Multiphase ultra low k dielectric material
02/21/2013US20130043470 Crack stop structure and method for forming the same
02/21/2013US20130042912 Solder bonded body, method of producing solder bonded body, element, photovoltaic cell, method of producing element and method of producing photovoltaic cell
02/21/2013DE102012213407A1 Halbleiteranordnung Semiconductor device
02/21/2013DE102012107403A1 Chip-Gehäuse-Modul für einen Chip und ein Verfahren zum Herstellen eines Chip-Gehäuse-Moduls Chip package for a chip module and a method of manufacturing a chip package module
02/21/2013DE102012105764A1 Housing stack structure for wireless mobile phone, has intermediate housing terminals to transfer data signals and address/control signals and to provide power supply voltage for address/control circuit and data circuit, respectively
02/21/2013DE102011111032A1 Method for manufacturing power-semiconductor module, involves copper layer made of electrically conductive material differs from material and isolated on connecting surfaces and bonding wires
02/21/2013DE102011081100A1 Anordnung mit Photozellen Arrangement with photocell
02/21/2013DE102009019313B4 Anordnung und Verfahren zum Kühlen einer wärmeerzeugenden Baueinheit Apparatus and method for cooling a heat generating unit
02/21/2013DE102008025599B4 Gehäuste aktive Mikrostrukturen mit Direktkontaktierung zu einem Substrat Packaged active microstructures with direct contacting a substrate
02/21/2013DE102005010337B4 Bauelementanordnung mit einem Bipolartransistor und einem Lastunterbrechungsdetektor Component arrangement with a bipolar transistor and a load interruption detector
02/21/2013CA2844789A1 Semiconductor laser mounting with intact diffusion barrier layer
02/21/2013CA2844563A1 Mixing manifold and method
02/20/2013EP2560204A2 Power semiconducter module and semiconducter module assembly with multiple power semiconducter modules
02/20/2013EP2560203A1 Power semiconductor arrangement
02/20/2013EP2560202A2 Heat sinking plate